SPRS717 Data sheet | TI.com

SPRS717L October 2011 – March 2020 AM3351 , AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3359

PRODUCTION DATA.

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

ZCZ|324

Thermal pad, mechanical data (Package|Pins)

Orderable Information

5.4 Operating Performance Points (OPPs)

Device OPPs are defined in Table 5-2 through Table 5-9.

Table 5-2 VDD_CORE OPPs for ZCZ Package
Device Rev. "A or Newer"⁽¹⁾

VDD_CORE OPP Device Rev. "A or Newer"		VDD_CORE			DDR3, DDR3L⁽²⁾	DDR2⁽²⁾	mDDR⁽²⁾	L3 and L4
VDD_CORE OPP Device Rev. "A or Newer"		MIN	NOM	MAX	DDR3, DDR3L⁽²⁾	DDR2⁽²⁾	mDDR⁽²⁾	L3 and L4
OPP100		1.056 V	1.100 V	1.144 V	400 MHz	266 MHz	200 MHz	200 and 100 MHz
OPP50		0.912 V	0.950 V	0.988 V	—	125 MHz	90 MHz	100 and 50 MHz

Frequencies in this table indicate maximum performance for a given OPP condition.
This parameter represents the maximum memory clock frequency. Because data is transferred on both edges of the clock, double-data rate (DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.

Table 5-3 VDD_MPU OPPs for ZCZ Package
With Device Revision Code "Blank"⁽¹⁾

VDD_MPU OPP Device Rev. "Blank"	VDD_MPU			ARM (A8)
VDD_MPU OPP Device Rev. "Blank"	MIN	NOM	MAX	ARM (A8)
Turbo	1.210 V	1.260 V	1.326 V	720 MHz
OPP120	1.152 V	1.200 V	1.248 V	600 MHz
OPP100⁽²⁾	1.056 V	1.100 V	1.144 V	500 MHz
OPP100⁽³⁾	1.056 V	1.100 V	1.144 V	275 MHz

Frequencies in this table indicate maximum performance for a given OPP condition.
Applies to all orderable AM335__ZCZ_50 (500-MHz speed grade) or higher devices.
Applies to all orderable AM335__ZCZ_27 (275-MHz speed grade) devices.

Table 5-4 Valid Combinations of VDD_CORE and VDD_MPU OPPs for ZCZ Package
With Device Revision Code "Blank"

VDD_CORE	VDD_MPU
OPP50	OPP100
OPP100	OPP100
OPP100	OPP120
OPP100	Turbo

Table 5-5 VDD_CORE OPPs for ZCE Package
With Device Revision Code "Blank"⁽¹⁾

VDD_CORE OPP Device Rev. "Blank"	VDD_MPU⁽²⁾			ARM (A8)	DDR3, DDR3L⁽³⁾	DDR2⁽³⁾	mDDR⁽³⁾	L3 and L4
VDD_CORE OPP Device Rev. "Blank"	MIN	NOM	MAX	ARM (A8)	DDR3, DDR3L⁽³⁾	DDR2⁽³⁾	mDDR⁽³⁾	L3 and L4
OPP100	1.056 V	1.100 V	1.144 V	500 MHz	400 MHz	266 MHz	200 MHz	200 and 100 MHz
OPP100	1.056 V	1.100 V	1.144 V	275 MHz	400 MHz	266 MHz	200 MHz	200 and 100 MHz

Frequencies in this table indicate maximum performance for a given OPP condition.
VDD_MPU is merged with VDD_CORE on the ZCE package.
This parameter represents the maximum memory clock frequency. Because data is transferred on both edges of the clock, double-data rate (DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.

Table 5-6 VDD_CORE OPPs for ZCZ Package
With Device Revision Code "A" or Newer⁽¹⁾

VDD_CORE OPP Rev "A" or Newer		VDD_CORE			DDR3, DDR3L⁽²⁾	DDR2⁽²⁾	mDDR⁽²⁾	L3 and L4
VDD_CORE OPP Rev "A" or Newer		MIN	NOM	MAX	DDR3, DDR3L⁽²⁾	DDR2⁽²⁾	mDDR⁽²⁾	L3 and L4
OPP100	Industrial extended temperature (–40°C to 125°C)	1.056 V	1.100 V	1.144 V	333 MHz	266 MHz	200 MHz	200 and 100 MHz
OPP100	All other temperature ranges	1.056 V	1.100 V	1.144 V	400 MHz	266 MHz	200 MHz	200 and 100 MHz
OPP50	Industrial extended temperature (–40°C to 125°C)	0.912 V	0.950 V	0.988 V	—	125 MHz	90 MHz	100 and 50 MHz
OPP50	All other temperature ranges	0.912 V	0.950 V	0.988 V	—	125 MHz	90 MHz	100 and 50 MHz

Frequencies in this table indicate maximum performance for a given OPP condition.
This parameter represents the maximum memory clock frequency. Because data is transferred on both edges of the clock, double-data rate (DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.

Table 5-7 VDD_MPU OPPs for ZCZ Package
With Device Revision Code "A" or Newer⁽¹⁾

VDD_MPU OPP Rev "A" or Newer	VDD_MPU			ARM (A8)
VDD_MPU OPP Rev "A" or Newer	MIN	NOM	MAX	ARM (A8)
Nitro	1.272 V	1.325 V	1.378 V	1 GHz
Turbo	1.210 V	1.260 V	1.326 V	800 MHz
OPP120	1.152 V	1.200 V	1.248 V	720 MHz
OPP100⁽²⁾	1.056 V	1.100 V	1.144 V	600 MHz
OPP100⁽³⁾	1.056 V	1.100 V	1.144 V	300 MHz
OPP50	0.912 V	0.950 V	0.988 V	300 MHz

Frequencies in this table indicate maximum performance for a given OPP condition.
Applies to all orderable AM335__ZCZ_60 (600-MHz speed grade) or higher devices.
Applies to all orderable AM335__ZCZ_30 (300-MHz speed grade) devices.

Table 5-8 Valid Combinations of VDD_CORE and VDD_MPU OPPs for ZCZ Package With Device Revision Code "A" or Newer

VDD_CORE	VDD_MPU
OPP50	OPP50
OPP50	OPP100
OPP100	OPP50
OPP100	OPP100
OPP100	OPP120
OPP100	Turbo
OPP100	Nitro

Table 5-9 VDD_CORE OPPs for ZCE Package
With Device Revision Code "A" or Newer⁽¹⁾

VDD_CORE OPP Rev "A" or newer	VDD_MPU⁽²⁾			ARM (A8)	DDR3, DDR3L⁽³⁾	DDR2⁽³⁾	mDDR⁽³⁾	L3 and L4
VDD_CORE OPP Rev "A" or newer	MIN	NOM	MAX	ARM (A8)	DDR3, DDR3L⁽³⁾	DDR2⁽³⁾	mDDR⁽³⁾	L3 and L4
OPP100	1.056 V	1.100 V	1.144 V	600 MHz	400 MHz	266 MHz	200 MHz	200 and 100 MHz
OPP100	1.056 V	1.100 V	1.144 V	300 MHz	400 MHz	266 MHz	200 MHz	200 and 100 MHz
OPP50	0.912 V	0.950 V	0.988 V	300 MHz	–	125 MHz	90 MHz	100 and 50 MHz

Frequencies in this table indicate maximum performance for a given OPP condition.
VDD_MPU is merged with VDD_CORE on the ZCE package.
This parameter represents the maximum memory clock frequency. Because data is transferred on both edges of the clock, double-data rate (DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.