SLUSC35B April 2015 – April 2019 AM3358-EP
PRODUCTION DATA.
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VDD_MPU | Supply voltage for the MPU core domain | –0.5 | 1.5 | V | |
VDD_CORE | Supply voltage for the core domain | –0.5 | 1.5 | V | |
CAP_VDD_RTC(3) | Supply voltage for the RTC core domain | –0.5 | 1.5 | V | |
VPP(4) | Supply voltage for the FUSE ROM domain | –0.5 | 2.2 | V | |
VDDS_RTC | Supply voltage for the RTC domain | –0.5 | 2.1 | V | |
VDDS_OSC | Supply voltage for the System oscillator | –0.5 | 2.1 | V | |
VDDS_SRAM_CORE_BG | Supply voltage for the Core SRAM LDOs | –0.5 | 2.1 | V | |
VDDS_SRAM_MPU_BB | Supply voltage for the MPU SRAM LDOs | –0.5 | 2.1 | V | |
VDDS_PLL_DDR | Supply voltage for the DPLL DDR | –0.5 | 2.1 | V | |
VDDS_PLL_CORE_LCD | Supply voltage for the DPLL Core and LCD | –0.5 | 2.1 | V | |
VDDS_PLL_MPU | Supply voltage for the DPLL MPU | –0.5 | 2.1 | V | |
VDDS_DDR | Supply voltage for the DDR I/O domain | –0.5 | 2.1 | V | |
VDDS | Supply voltage for all dual-voltage I/O domains | –0.5 | 2.1 | V | |
VDDA1P8V_USB0 | Supply voltage for USBPHY | –0.5 | 2.1 | V | |
VDDA1P8V_USB1 | Supply voltage for USBPHY | –0.5 | 2.1 | V | |
VDDA_ADC | Supply voltage for ADC | –0.5 | 2.1 | V | |
VDDSHV1 | Supply voltage for the dual-voltage I/O domain | –0.5 | 3.8 | V | |
VDDSHV2 | Supply voltage for the dual-voltage I/O domain | –0.5 | 3.8 | V | |
VDDSHV3 | Supply voltage for the dual-voltage I/O domain | –0.5 | 3.8 | V | |
VDDSHV4 | Supply voltage for the dual-voltage I/O domain | –0.5 | 3.8 | V | |
VDDSHV5 | Supply voltage for the dual-voltage I/O domain | –0.5 | 3.8 | V | |
VDDSHV6 | Supply voltage for the dual-voltage I/O domain | –0.5 | 3.8 | V | |
VDDA3P3V_USB0 | Supply voltage for USBPHY | –0.5 | 4 | V | |
VDDA3P3V_USB1 | Supply voltage for USBPHY | –0.5 | 4 | V | |
USB0_VBUS(5) | Supply voltage for USB VBUS comparator input | –0.5 | 5.25 | V | |
USB1_VBUS(5) | Supply voltage for USB VBUS comparator input | –0.5 | 5.25 | V | |
DDR_VREF | Supply voltage for the DDR SSTL and HSTL reference voltage | –0.3 | 1.1 | V | |
Steady state max voltage at all I/O pins(6) | –0.5 V to I/O supply voltage + 0.3 V | ||||
USB0_ID(7) | Steady state maximum voltage for the USB ID input | –0.5 | 2.1 | V | |
USB1_ID(7) | Steady state maximum voltage for the USB ID input | –0.5 | 2.1 | V | |
Transient overshoot and undershoot specification at I/O terminal | 25% of corresponding I/O supply voltage for up to 30% of signal period | ||||
Latch-up performance(8) | Class II (105°C) | 45 | mA | ||
Class II (125°C) | 1.8-V mode | –100 | 100 | mA | |
3.3-V mode; applies to all I/O pins except those included in latch-up pin groups A, B, and C | –100 | 100 | |||
3.3-V mode; applies to latch-up pin group A | –35 | 100 | |||
3.3-V mode; applies to latch-up pin group B | –45 | 75 | |||
3.3-V mode; applies to latch-up pin group C | –100 | 70 | |||
Junction temperature, TJ | –40 | 125 | °C | ||
Storage temperature, Tstg(9) | –55 | 155 | °C |
Fail-safe I/O terminals are designed such they do not have dependencies on the respective I/O power supply voltage. This allows external voltage sources to be connected to these I/O terminals when the respective I/O power supplies are turned off. The USB0_VBUS and USB1_VBUS are the only fail-safe I/O terminals. All other I/O terminals are not fail-safe and the voltage applied to them should be limited to the value defined by the steady state max. Voltage at all I/O pins parameter in Section 5.1.