SLUSC35B
April 2015 – April 2019
AM3358-EP
PRODUCTION DATA.
1
Device Overview
1.1
Features
1.2
Applications
1.3
Description
1.4
Functional Block Diagram
2
Revision History
3
Device Features
3.1
Related Products
4
Terminal Configuration and Functions
4.1
Pin Diagram
4.1.1
GCZ Package Pin Maps (Top View)
GCZ Pin Map [Section Left - Top View]
GCZ Pin Map [Section Middle - Top View]
GCZ Pin Map [Section Right - Top View]
4.2
Pin Attributes
4.3
Signal Descriptions
4.3.1
External Memory Interfaces
4.3.2
General Purpose IOs
4.3.3
Miscellaneous
4.3.3.1
eCAP
4.3.3.2
eHRPWM
4.3.3.3
eQEP
4.3.3.4
Timer
4.3.4
PRU-ICSS
4.3.4.1
PRU0
4.3.4.2
PRU1
4.3.5
Removable Media Interfaces
4.3.6
Serial Communication Interfaces
4.3.6.1
CAN
4.3.6.2
GEMAC_CPSW
4.3.6.3
I2C
4.3.6.4
McASP
4.3.6.5
SPI
4.3.6.6
UART
4.3.6.7
USB
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Power-On Hours (POH)
5.4
Operating Performance Points (OPPs)
5.5
Recommended Operating Conditions
5.6
Power Consumption Summary
5.7
DC Electrical Characteristics
5.8
Thermal Resistance Characteristics for GCZ Package
5.9
External Capacitors
5.9.1
Voltage Decoupling Capacitors
5.9.1.1
Core Voltage Decoupling Capacitors
5.9.1.2
I/O and Analog Voltage Decoupling Capacitors
5.9.2
Output Capacitors
5.10
Touch Screen Controller and Analog-to-Digital Subsystem Electrical Parameters
6
Power and Clocking
6.1
Power Supplies
6.1.1
Power Supply Slew Rate Requirement
6.1.2
Power-Down Sequencing
6.1.3
VDD_MPU_MON Connections
6.1.4
Digital Phase-Locked Loop Power Supply Requirements
6.2
Clock Specifications
6.2.1
Input Clock Specifications
6.2.2
Input Clock Requirements
6.2.2.1
OSC0 Internal Oscillator Clock Source
Table 6-2
OSC0 Crystal Circuit Requirements
Table 6-3
OSC0 Crystal Circuit Characteristics
6.2.2.2
OSC0 LVCMOS Digital Clock Source
6.2.2.3
OSC1 Internal Oscillator Clock Source
Table 6-5
OSC1 Crystal Circuit Requirements
Table 6-6
OSC1 Crystal Circuit Characteristics
6.2.2.4
OSC1 LVCMOS Digital Clock Source
6.2.2.5
OSC1 Not Used
6.2.3
Output Clock Specifications
6.2.4
Output Clock Characteristics
6.2.4.1
CLKOUT1
6.2.4.2
CLKOUT2
7
Peripheral Information and Timings
7.1
Parameter Information
7.1.1
Timing Parameters and Board Routing Analysis
7.2
Recommended Clock and Control Signal Transition Behavior
7.3
OPP50 Support
7.4
Controller Area Network (CAN)
7.4.1
DCAN Electrical Data and Timing
Table 7-1
DCAN Timing Conditions
Table 7-2
Timing Requirements for DCANx Receive
Table 7-3
Switching Characteristics for DCANx Transmit
7.5
DMTimer
7.5.1
DMTimer Electrical Data and Timing
Table 7-4
DMTimer Timing Conditions
Table 7-5
Timing Requirements for DMTimer [1-7]
Table 7-6
Switching Characteristics for DMTimer [4-7]
7.6
Ethernet Media Access Controller (EMAC) and Switch
7.6.1
EMAC and Switch Electrical Data and Timing
Table 7-7
EMAC and Switch Timing Conditions
7.6.1.1
EMAC/Switch MDIO Electrical Data and Timing
Table 7-8
Timing Requirements for MDIO_DATA
Table 7-9
Switching Characteristics for MDIO_CLK
Table 7-10
Switching Characteristics for MDIO_DATA
7.6.1.2
EMAC and Switch MII Electrical Data and Timing
Table 7-11
Timing Requirements for GMII[x]_RXCLK - MII Mode
Table 7-12
Timing Requirements for GMII[x]_TXCLK - MII Mode
Table 7-13
Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode
Table 7-14
Switching Characteristics for GMII[x]_TXD[3:0], and GMII[x]_TXEN - MII Mode
7.6.1.3
EMAC and Switch RMII Electrical Data and Timing
Table 7-15
Timing Requirements for RMII[x]_REFCLK - RMII Mode
Table 7-16
Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
Table 7-17
Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
7.6.1.4
EMAC and Switch RGMII Electrical Data and Timing
Table 7-18
Timing Requirements for RGMII[x]_RCLK - RGMII Mode
Table 7-19
Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
Table 7-20
Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
Table 7-21
Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
7.7
External Memory Interfaces
7.7.1
General-Purpose Memory Controller (GPMC)
7.7.1.1
GPMC and NOR Flash—Synchronous Mode
Table 7-22
GPMC and NOR Flash Timing Conditions—Synchronous Mode
Table 7-23
GPMC and NOR Flash Timing Requirements—Synchronous Mode
Table 7-24
GPMC and NOR Flash Switching Characteristics—Synchronous Mode
7.7.1.2
GPMC and NOR Flash—Asynchronous Mode
Table 7-25
GPMC and NOR Flash Timing Conditions—Asynchronous Mode
Table 7-26
GPMC and NOR Flash Internal Timing Requirements—Asynchronous Mode
Table 7-27
GPMC and NOR Flash Timing Requirements—Asynchronous Mode
Table 7-28
GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
7.7.1.3
GPMC and NAND Flash—Asynchronous Mode
Table 7-29
GPMC and NAND Flash Timing Conditions—Asynchronous Mode
Table 7-30
GPMC and NAND Flash Internal Timing Requirements—Asynchronous Mode
Table 7-31
GPMC and NAND Flash Timing Requirements—Asynchronous Mode
Table 7-32
GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
7.7.2
mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface
7.7.2.1
mDDR (LPDDR) Routing Guidelines
7.7.2.1.1
Board Designs
7.7.2.1.2
LPDDR Interface
7.7.2.1.2.1
LPDDR Interface Schematic
7.7.2.1.2.2
Compatible JEDEC LPDDR Devices
Table 7-34
Compatible JEDEC LPDDR Devices (Per Interface)
7.7.2.1.2.3
PCB Stackup
7.7.2.1.2.4
Placement
7.7.2.1.2.5
LPDDR Keepout Region
7.7.2.1.2.6
Bulk Bypass Capacitors
7.7.2.1.2.7
High-Speed Bypass Capacitors
7.7.2.1.2.8
Net Classes
7.7.2.1.2.9
LPDDR Signal Termination
7.7.2.1.3
LPDDR CK and ADDR_CTRL Routing
7.7.2.2
DDR2 Routing Guidelines
7.7.2.2.1
Board Designs
7.7.2.2.2
DDR2 Interface
7.7.2.2.2.1
DDR2 Interface Schematic
7.7.2.2.2.2
Compatible JEDEC DDR2 Devices
Table 7-46
Compatible JEDEC DDR2 Devices (Per Interface)
7.7.2.2.2.3
PCB Stackup
7.7.2.2.2.4
Placement
7.7.2.2.2.5
DDR2 Keepout Region
7.7.2.2.2.6
Bulk Bypass Capacitors
7.7.2.2.2.7
High-Speed (HS) Bypass Capacitors
7.7.2.2.2.8
Net Classes
7.7.2.2.2.9
DDR2 Signal Termination
7.7.2.2.2.10
DDR_VREF Routing
7.7.2.2.3
DDR2 CK and ADDR_CTRL Routing
7.7.2.3
DDR3 and DDR3L Routing Guidelines
7.7.2.3.1
Board Designs
7.7.2.3.1.1
DDR3 versus DDR2
7.7.2.3.2
DDR3 Device Combinations
7.7.2.3.3
DDR3 Interface
7.7.2.3.3.1
DDR3 Interface Schematic
7.7.2.3.3.2
Compatible JEDEC DDR3 Devices
7.7.2.3.3.3
PCB Stackup
7.7.2.3.3.4
Placement
7.7.2.3.3.5
DDR3 Keepout Region
7.7.2.3.3.6
Bulk Bypass Capacitors
7.7.2.3.3.7
High-Speed Bypass Capacitors
7.7.2.3.3.7.1
Return Current Bypass Capacitors
7.7.2.3.3.8
Net Classes
7.7.2.3.3.9
DDR3 Signal Termination
7.7.2.3.3.10
DDR_VREF Routing
7.7.2.3.3.11
VTT
7.7.2.3.4
DDR3 CK and ADDR_CTRL Topologies and Routing Definition
7.7.2.3.4.1
Two DDR3 Devices
7.7.2.3.4.1.1
CK and ADDR_CTRL Topologies, Two DDR3 Devices
7.7.2.3.4.1.2
CK and ADDR_CTRL Routing, Two DDR3 Devices
7.7.2.3.4.2
One DDR3 Device
7.7.2.3.4.2.1
CK and ADDR_CTRL Topologies, One DDR3 Device
7.7.2.3.4.2.2
CK and ADDR_CTRL Routing, One DDR3 Device
7.7.2.3.5
Data Topologies and Routing Definition
7.7.2.3.5.1
DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices
7.7.2.3.5.2
DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices
7.7.2.3.6
Routing Specification
7.7.2.3.6.1
CK and ADDR_CTRL Routing Specification
7.7.2.3.6.2
DQS[x] and DQ[x] Routing Specification
7.8
I2C
7.8.1
I2C Electrical Data and Timing
Table 7-70
I2C Timing Conditions – Slave Mode
Table 7-71
Timing Requirements for I2C Input Timings
Table 7-72
Switching Characteristics for I2C Output Timings
7.9
JTAG Electrical Data and Timing
Table 7-73
JTAG Timing Conditions
Table 7-74
Timing Requirements for JTAG
Table 7-75
Switching Characteristics for JTAG
7.10
LCD Controller (LCDC)
Table 7-76
LCD Controller Timing Conditions
7.10.1
LCD Interface Display Driver (LIDD Mode)
Table 7-77
Timing Requirements for LCD LIDD Mode
Table 7-78
Switching Characteristics for LCD LIDD Mode
7.10.2
LCD Raster Mode
Table 7-79
Switching Characteristics for LCD Raster Mode
7.11
Multichannel Audio Serial Port (McASP)
7.11.1
McASP Device-Specific Information
7.11.2
McASP Electrical Data and Timing
Table 7-80
McASP Timing Conditions
Table 7-81
Timing Requirements for McASP
Table 7-82
Switching Characteristics for McASP
7.12
Multichannel Serial Port Interface (McSPI)
7.12.1
McSPI Electrical Data and Timing
7.12.1.1
McSPI—Slave Mode
Table 7-83
McSPI Timing Conditions – Slave Mode
Table 7-84
Timing Requirements for McSPI Input Timings—Slave Mode
Table 7-85
Switching Characteristics for McSPI Output Timings—Slave Mode
7.12.1.2
McSPI—Master Mode
Table 7-86
McSPI Timing Conditions – Master Mode
Table 7-87
Timing Requirements for McSPI Input Timings – Master Mode
Table 7-88
Switching Characteristics for McSPI Output Timings – Master Mode
7.13
Multimedia Card (MMC) Interface
7.13.1
MMC Electrical Data and Timing
Table 7-89
MMC Timing Conditions
Table 7-90
Timing Requirements for MMC[x]_CMD and MMC[x]_DAT[7:0]
Table 7-91
Switching Characteristics for MMC[x]_CLK
Table 7-92
Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—Standard Mode
Table 7-93
Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—High-Speed Mode
7.14
Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
7.14.1
Programmable Real-Time Unit (PRU-ICSS PRU)
Table 7-94
PRU-ICSS PRU Timing Conditions
7.14.1.1
PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
Table 7-95
PRU-ICSS PRU Timing Requirements - Direct Input Mode
Table 7-96
PRU-ICSS PRU Switching Requirements – Direct Output Mode
7.14.1.2
PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
Table 7-97
PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
7.14.1.3
PRU-ICSS PRU Shift Mode Electrical Data and Timing
Table 7-98
PRU-ICSS PRU Timing Requirements – Shift In Mode
Table 7-99
PRU-ICSS PRU Switching Requirements - Shift Out Mode
7.14.2
PRU-ICSS MII_RT and Switch
Table 7-100
PRU-ICSS MII_RT Switch Timing Conditions
7.14.2.1
PRU-ICSS MDIO Electrical Data and Timing
Table 7-101
PRU-ICSS MDIO Timing Requirements – MDIO_DATA
Table 7-102
PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
Table 7-103
PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
7.14.2.2
PRU-ICSS MII_RT Electrical Data and Timing
Table 7-104
PRU-ICSS MII_RT Timing Requirements – MII_RXCLK
Table 7-105
PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
Table 7-106
PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
Table 7-107
PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
7.14.3
PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
Table 7-108
UART Timing Conditions
Table 7-109
Timing Requirements for PRU-ICSS UART Receive
Table 7-110
Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
7.15
Universal Asynchronous Receiver Transmitter (UART)
7.15.1
UART Electrical Data and Timing
Table 7-111
Timing Requirements for UARTx Receive
Table 7-112
Switching Characteristics for UARTx Transmit
7.15.2
UART IrDA Interface
8
Device and Documentation Support
8.1
Device Nomenclature
8.2
Tools and Software
8.3
Documentation Support
8.4
Community Resources
8.5
Trademarks
8.6
Electrostatic Discharge Caution
8.7
Glossary
9
Mechanical, Packaging, and Orderable Information
9.1
Via Channel
9.2
Packaging Information
Package Options
Mechanical Data (Package|Pins)
GCZ|324
MPBGAK5
Thermal pad, mechanical data (Package|Pins)
Orderable Information
SLUSC35B_pm
slusc35b_oa
9
Mechanical, Packaging, and Orderable Information