6.2.1 Voltage and Power Domains

Every Module within the device belongs to a Core Logic Voltage Domain, Memory Voltage Domain, and a Power Domain (see Table 6-1).

6.2.2 SmartReflex [Not Supported]

The device contains SmartReflex modules that help to minimize power consumption on the Core Logic Voltage Domains by using external variable-voltage power supplies. Based on the device process, temperature, and desired performance, the SmartReflex modules advise the host processor to raise or lower the supply voltage to each domain for minimal power consumption.

The communication link between the host processor and the external regulators is a system-level decision and can be accomplished using GPIOs, I2C, SPI, or other methods. The following sections briefly describe the two major techniques employed by SmartReflex: Dynamic Voltage Frequency Scaling (DVFS) and Adaptive Voltage Scaling (AVS).

6.2.3 Memory Power Management

To reduce SRAM leakage, many SRAM blocks can be switched from ACTIVE mode to SHUTDOWN mode. When SRAM is put in SHUTDOWN mode, the voltage supplied to it is automatically removed and all data in that SRAM is lost.

All SRAM located in a switchable power domain (all domains except ALWAYS_ON) automatically enters SHUTDOWN mode whenever its associated power domain goes into the "OFF" state. The SRAM returns to the ACTIVE state when the corresponding Power Domain returns to the "ON" state.

In addition, the following SRAM within the ALWAYS_ON Power Domain can also be independently put into SHUTDOWN by programming the x_MEM_PWRDN registers in the Control Module:

• Media Controller SRAM
• OCMC SRAM

For detailed instructions on powering up/down the various device SRAM, see the Control Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

6.2.4 SERDES_CLKP and SERDES_CLKN LDO

The SERDES_CLKP and SERDES_CLKN input buffers are powered by an internal LDO which is programmed through the REFCLK_LJCBLDO_CTRL register in the Control Module.

For more information on programming the SERDES_CLKP and SERDES_CLKN LDO, see PCI Express (PCIe) Module and Serial ATA (SATA) Controller chapters of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

6.2.5 Dual Voltage I/Os

The device supports dual voltages on some of its I/Os. These I/Os are partitioned into the following groups, and each group has its own dedicated supply pins: DVDD, DVDD_GPMC, DVDD_C, and DVDD_SD. The supply voltage for each group can be independently powered with either 1.8 V or 3.3 V.

For the mapping between pins and power groups, see Section 2.11.

In addition, the I/O voltage on each DDR interface is independently selectable between either 1.5 V or 1.8 V to support various DDR device types. The I/O supplies for each DDR interface are separate and isolated to allow populating different memory types on each interface.

6.2.6 I/O Power-Down Modes

On the device, there are power-down modes available for the following PHYs:

• Video DAC
• DDR
• USB
• HDMI
• PCIE
• SATA

When a PHY controller is in a power domain that is to be turned "OFF", software must configure the corresponding PHY into power-down mode, prior to putting the power domain in the "OFF" state.

6.2.7 Standby Mode

The device supports Low-Power Standby Mode as described below.

Standby Mode is defined as a state in which:

• All switchable power domains are in "OFF" state
• The ARM Cortex-A8 is executing an IDLE loop at its lowest frequency of operation
• All functional blocks not needed for a given application are clock gated

For detailed instructions on entering and exiting from Standby Mode see the Power, Reset, and Clock Management (PRCM) Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

6.2.8 Supply Sequencing

The device power supplies are organized into four Supply Sequencing Groups:

1. All CVDD supplies (CVDD, CVDD_x)
2. All 1.5-/1.8-V DVDD_DDR[x] Supplies (1.5 V for DDR3, 1.8 V for DDR2)
3. All 1.8-V Supplies (DVDD_x, DVDD_M, VDDA_x_1P8, VDDA_1P8)
4. All 3.3-V Supplies (DVDD, DVDD_x, DVDD_C, VDDA_x_3P3)

To ensure proper device operation, a specific power-up and power-down sequence must be followed. Some TI power-supply devices include features that facilitate these power sequencing requirements — for example, TI’s TPS659113 integrated PMIC. For more information on TI power supplies and their features, visit www.ti.com/processorpower.

For more detailed information on the actual power supply names and their descriptions, see Table 2-49, Supply Voltages Terminal Functions.

6.2.8.1 Power-Up Sequence

For proper device operation, the following power-up sequence in Table 6-6 and must be followed.

Table 6-6 Power-Up Sequence Ramping Values

NO.	DESCRIPTION	MIN	MAX	UNIT
1	1.8 V and DVDD_DDR[x] supplies stable to 3.3 V supplies ramp start	0		ms
2	1.8 V supplies to 1.5-/1.8- V DVDD_DDR[x] supplies	0(1)		ms
3	1.8 V supplies stable to CVDD, CVDD_x variable supplies ramp start	0(1)		ms
13	CVDD variable supply ramp start to CVDD_x variable supplies ramp start	0		ms
4	All supplies valid to power-on-reset (POR high)	4 096		Master Clocks

(1) The 1.8 V supplies must be ≥ 1.5-/1.8-V DVDD_DDR[x] supplies.

Figure 6-1 Power-Up Sequence

6.2.8.2 Power-Down Sequence

For proper device operation, the following power-down sequence in Table 6-7 and Figure 6-2 must be followed. Ramping down all supplies at the same time is allowed, provided the requirements in Table 6-7 are met.

Table 6-7 Power-Down Sequence Ramping Values

NO.	DESCRIPTION	MIN	MAX	UNIT
8	CVDD, CVDD_x variable supply to 1.8 V supplies	See (2)	See (2)	ms
9	1.5-/1.8-V DVDD_DDR[x] supplies to 1.8 V supplies	See (2)	See (2)	ms
10	3.3 V supplies to 1.8 V supplies	See (1)	See (1)	ms
14	CVDD_x variable supplies ramp-down start to CVDD variable supply ramp-down start	0		ms

(1) The 3.3 V supplies must never be more than 2 V above the 1.8 V supplies (see Figure 6-3).

(2) The 1.5-/1.8-V DVDD_DDR[x] and CVDD, CVDD_x variable supplies can be powered down prior to or simultaneously with the 1.8-V supplies.

Figure 6-2 Power-Down Sequence

Figure 6-3 1.8 V Supplies Falling Before 3.3 V Supplies Delta

6.2.9 Power-Supply Decoupling

6.3.1 System-Level Reset Sources

The device has several types of system-level resets. Table 6-8 lists these reset types, along with the reset initiator, and the effects of each reset on the device.

6.3.2 Power-on Reset (POR pin)

Power-on Reset (POR) is initiated by the POR pin and is used to reset the entire chip, including the Test and Emulation logic, and the EMAC Switch. POR is also referred to as a cold reset because it is required to be asserted when the device goes through a power-up cycle. However, a device power-up cycle is not required to initiate a Power-on Reset.

The following sequence must be followed during a Power-on Reset:

1. Wait for the power supplies to reach normal operating conditions while keeping the POR pin asserted.
2. Wait for the input clock sources DEV_CLKIN, AUX_CLKIN, and SERDES_CLKN/P to be stable (if used by the system) while keeping the POR pin asserted (low).
3. Once the power supplies and the input clock sources are stable, the POR pin must remain asserted (low) [see Section 6.3.18, Reset Electrical Data/Timing]. Within the low period of the POR pin, the following happens:
   1. All pins except Emulation pins enter a Hi-Z mode and the associated pulls, if applicable, will be enabled.
   2. The PRCM asserts reset to all modules within the device.
   3. The PRCM begins propagating these clocks to the chip with the PLLs in BYPASS mode.
4. The POR pin may now be deasserted (driven high). When the POR pin is deasserted (high):
   1. The BTMODE[15:0] pins are latched.
   2. Reset to the ARM Cortex-A8 and Modules without a local processor is deasserted.
   3. RSTOUT_WD_OUT is briefly asserted if BTMODE[11] was latched as "0".
   4. The clock, reset, and power-down state of each peripheral is determined by the default settings of the PRCM.
   5. The ARM Cortex-A8 begins executing from the Boot ROM.

6.3.3 External Warm Reset (RESET pin)

An external warm reset is activated by driving the RESET pin active-low. This resets everything in the device, except for the Test and Emulation logic, and the EMAC Switch (optional). An emulator session stays alive during warm reset.

The following sequence must be followed during a warm reset:

1. Power supplies and input clock sources should already be stable.
2. The RESET pin must be asserted (low)[see Section 6.3.18, Reset Electrical Data/Timing]. Within the low period of the RESET pin, the following happens:
   1. All pins, except Test and Emulation pins, enter a Hi-Z mode and the associated pulls, if applicable, will be enabled.
   2. The PRCM asserts reset to all modules within the device, except for the Test and Emulation logic, EMAC Switch (optional), PLL, and Clock configuration.
3. The RESET pin may now be deasserted (driven high). When the RESET pin is deasserted (high):
   1. The BTMODE[15:0] pins are latched.
   2. Reset to the ARM Cortex-A8 and modules without a local processor is deasserted, with the exception of Test and Emulation logic, EMAC Switch (optional), PLL, and Clock configuration.
   3. RSTOUT_WD_OUT is asserted [see Section 6.3.18, Reset Electrical Data/Timing], if BTMODE[11] was latched as "0".
   4. The clock, reset, and power-down state of each peripheral is determined by the default settings of the PRCM.
   5. The ARM Cortex-A8 begins executing from the Boot ROM.

6.3.4 Emulation Warm Reset

An Emulation Warm Reset is activated by the on-chip Emulation Module and has the same effect and requirements as an External Warm Reset (RESET), with the following exceptions:

• BTMODE[15:0] pins are not relatched
• RSTOUT_WD_OUT is not 3-stated and is actively driven based on the value previously latched on the BTMODE[11] pin.

The emulator initiates an Emulation Warm Reset via the ICEPICK module. To invoke the Emulation Warm Reset via the ICEPICK module, the user can perform the following from the Code Composer Studio™ IDE menu: Target -> Reset -> System Reset.

6.3.5 Watchdog Reset

A Watchdog Reset is initiated when the Watchdog Timer counter reaches zero and has the same effect and requirements as an External Warm Reset (RESET pin), with the following exceptions:

• BTMODE[15:0] pins are not relatched
• RSTOUT_WD_OUT is not 3-stated and is actively driven based on the value previously latched on the BTMODE[11] pin.

In addition, a Watchdog Reset always results in RSTOUT_WD_OUT being asserted, regardless of whether the BTMODE[11] pin was latched as "0" or "1".

6.3.6 Software Global Cold Reset

A Software Global Cold Reset is initiated under software control and has the same effect and requirements as a POR Reset, with the following exceptions:

• BTMODE[15:0] pins are not relatched and EMAC Switch (optional) is not reset
• RSTOUT_WD_OUT is not 3-stated and is actively driven based on the value previously latched on the BTMODE[11] pin.

Software initiates a Software Global Cold Reset by writing a "1" to the RST_GLOBAL_COLD_SW bit in the PRM_RSTCTRL register in the PRCM.

For more detailed information on the PRM_RSTCTRL register, see the PRCM Registers section of the Power, Reset, and Clock Management (PRCM) Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

6.3.7 Software Global Warm Reset

A Software Global Warm Reset is initiated under software control and has the same effect and requirements as a External Warm Reset (RESET pin), with the following exceptions:

• BTMODE[15:0] pins are not relatched
• RSTOUT_WD_OUT is not 3-stated and is actively driven based on the value previously latched on the BTMODE[11] pin.

Software initiates a Software Global Warm Reset by writing a "1" to the RST_GLOBAL_WARM_SW bit in the PRM_RSTCTRL register in the PRCM.

For more detailed information on the PRM_RSTCTRL register, see the PRCM Registers section of the Power, Reset, and Clock Management (PRCM) Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

6.3.8 Test Reset (TRST pin)

A Test Reset is activated by the emulator asserting the TRST pin. The only effect a Test Reset has is to reset the Test and Emulation Logic.

6.3.9 Local Reset

The Local Reset for various Modules within the device is controlled by programming the PRCM and/or the Peripheral Module’s internal registers. Only the associated Module is reset when a Local Reset is asserted, leaving the rest of the device unaffected.

For more details on Peripheral Local Resets, see the Reset Management section of the Power, Reset, and Clock Management (PRCM) Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

6.3.10 Reset Priority

If any of the above reset sources occur simultaneously, the device only processes the highest-priority reset request. The reset request priorities, from high-to-low, are as follows:

1. Power-on Reset (POR)
2. Test Reset (TRST)
3. External Warm Reset (RESET pin)
4. Emulation Warm Resets
5. Watchdog Reset
6. Software Global Cold/Warm Resets

6.3.11 Reset Status Register

The Reset Status Register (PRM_RSTST) contains information about the last reset that occurred in the system. For more information on this register, see the Power, Reset, and Clock Management (PRCM) Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

6.3.12 PCIE Reset Isolation

The device supports reset isolation for the PCI-Express (PCIE) module. This means that the PCI-Express Subsystem can be reset without resetting the rest of the device.

When the devcie is a PCI-Express Root Complex (RC), the PCIE Subsystem can be reset by software through the PRCM. Software should ensure that there are no ongoing PCIE transactions before asserting this reset by first taking the PCIE Subsystem into the IDLE state. After bringing the PCIE Subsystem out of reset, bus enumeration should be performed again and should treat all Endpoints (EP) as if they had just been connected.

When the device is a PCI-Express Endpoint (EP), the PCIE Subsystem will generate an interrupt when an in-band reset is received. Software should process this interrupt by putting the PCIE Subsystem in the IDLE state and then asserting the PCIE local reset through the PRCM.

All device level resets mentioned in the previous sections, except Test Reset, will also reset the PCIE Subsystem. Therefore, the PCIE peripheral should issue a Hot Reset to all downstream devices and re-enumerate the bus upon coming out of reset.

For more detailed information on reset isolation procedures, see the PCIe Reset Isolation section of the Power, Reset, and Clock Management (PRCM) Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

6.3.13 EMAC Switch Reset Isolation

The device supports reset isolation for the Ethernet Switch (EMAC Switch). This allows the device to undergo all resets listed in Section 6.3.1, System-Level Reset Sources, with the exception of POR Reset, without disrupting the Ethernet Switch or the traffic being routed through the switch during the reset condition. The following reset types can optionally provide an EMAC Switch reset isolation by setting the ISO_CONTROL bit in the RESET_ISO Control Module register to a "1":

• External Warm Reset
• Emulation Warm Reset
• Watchdog Reset
• Software Global Cold Reset
• Software Global Warm Reset

When one of above resets occurs and the Ethernet Switch (EMAC Switch) is programmed to be isolated:

• The switch function of the EMAC Switch and the PLL embedded in the SATA SERDES Module (which provides the reference clocks to the EMAC Switch) will not be reset.
• Several Control Module registers are not reset. For more details, see the description of the RESET_ISO register in the Control Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).
• The pin multiplexing of some of the EMAC Switch pins is unaffected. For more details, see the description of the RESET_ISO register in the Control Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

The EMAC Switch is always reset when:

• One of the above resets occurs and the Ethernet Switch is programmed to be “not isolated”
• A POR Reset occurs

6.3.14 RSTOUT_WD_OUT Pin

The RSTOUT_WD_OUT pin reflects device reset status and is deasserted (high) when the device is out reset. This output will always be asserted when a Watchdog Timer reset (Watchdog Reset) occurs. In addition, this output is always 3-stated and the internal pull resistor is disabled on this pin while POR and/or RESET is asserted; therefore, an external pullup/pulldown can be used to set the state of this pin (high/low) while POR and/or RESET is asserted. For more detailed information on external PUs/PDs, see Section 3.5.1, Pullup/Pulldown Resistors.

If the BTMODE[11] pin is latched as a "0" at the rising edge of POR or RESET, then RSTOUT_WD_OUT is also asserted when any of the below resets occur:

• Power-On Reset (asserted after the BTMODE[11] pin is latched)
• External Warm Reset (asserted after the BTMODE[11] pin is latched)
• Emulation Warm Reset
• Software Global Cold/Warm Reset

The RSTOUT_WD_OUT pin remains asserted until the PRCM releases the host ARM Cortex-A8 processor for reset.

6.3.15 Effect of Reset on Emulation and Trace

The device Emulation and Trace Logic will only be reset by the following sources:

• Power-On Reset
• Software Global Cold Reset
• Test Reset

Other than these three reset types, none of the other resets will affect the Emulation and Trace Logic. However, the multiplexing of the EMU[4:2] pins is reset by all system reset types except Test Reset.

6.3.16 Reset During Power Domain Switching

Each Power Domain has a dedicated Warm Reset and Cold Reset. Warm Reset for a Power Domain is asserted under either of the following two conditions:

1. An External Warm Reset, Emulation Warm Reset, or Software Global Warm Reset occurs
2. When that Power Domain switches from the "ON" state to the "OFF" state

Cold Reset for a Power Domain is asserted under either of the following two conditions:

1. Power-On Reset or Software Global Cold Reset occurs
2. When that Power Domain switches from the "OFF" state to the "ON" state

6.3.17 Pin Behaviors at Reset

When any reset, other than Test Reset, (all described in Section 6.3.1, System-Level Reset Sources) is asserted, all device I/O pins are reset into a Hi-Z state except for:

• Emulation Pins. These pins are only put into a Hi-Z state when Test Reset (TRST) is asserted.
• EMAC Switch Pins. These pins are always put into a Hi-Z state during Power-On Reset. However, some EMAC Switch pins will not be put into a Hi-Z state during the other reset modes when the ISO_CONTROL bit in the RESET_ISO register of the Control Module is programmed as a "1". For more details, see the description of the RESET_ISO register in the Control Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).
• RSTOUT_WD_OUT Pin during any reset types except for POR and RESET. For more detailed information on RSTOUT_WD_OUT pin behavior, see Section 6.3.14, RSTOUT_WD_OUT Pin.
• DDR[0]/[1] Address/Control Pins (CLK, CLK, CKE, WE, CS[1]/[0], RAS, CAS, ODT[1]/[0], RST, BA[2:0], A[14:0]). These pins are 3-stated during reset. However, these pins are then driven to the same value as their internal pull resistor reset value when reset is released (For the direction of the internal pull during reset, see the DDR[0]/[1] Terminal Functions tables in the Section 2.11.4, DDR2/DDR3 Memory Controller of this document).

In addition, the PINCNTL registers, which control pin multiplexing, enabling the IPUs/IPDs, and enabling the receiver, are reset to their default state. Again, enabling the EMAC Switch reset isolation prevents some PINCNTL registers from being reset.

For details on EMAC Switch reset isolation, see the descriptions of the RESET_ISO register and the PINCNTL registers in the Control Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

Internal pull-up/down (IPU/IPD) resistors are enabled during and immediately after reset as described in Section 2.11, Terminal Functions of this document.

6.3.18 Reset Electrical Data/Timing

Figure 6-4 shows the Power-Up Timing. Figure 6-5 shows the Warm Reset (RESET) Timing. Max Reset Timing is identical to Warm Reset Timing, except the BTMODE[15:0] pins are not relatched.

A. Power supplies and DEV_CLKIN/AUX_CLKIN must be stable before the start of t_w(RESET).

B. RSTOUT_WD_OUT only asserted if BTMODE[11] was latched as a "0" when coming out of reset.

C. For more detailed information on the RESET STATE of each pin, see Section 6.3.17, Pin Behaviors at Reset. Also see Section 2.11, Terminal Functions for the IPU/IPD settings during reset.

Figure 6-4 Power-Up Timing

A. RSTOUT_WD_OUT only asserted if BTMODE[11] was latched as a "0" when coming out of reset.

B. For more detailed information on the RESET STATE of each pin, see Section 6.3.17, Pin Behaviors at Reset. Also see Section 2.11, Terminal Functions for the IPU/IPD settings during reset.

Figure 6-5 Warm Reset (RESET) Timing

6.4.1 Device (DEV) and Auxiliary (AUX) Clock Inputs

The device provides two clock inputs, Device (DEVOSC_MXI/DEV_CLKIN) and Auxiliary (AUXOSC_MXI/AUX_CLKIN). The Device (DEV) clock is used to generate the majority of the internal reference clocks, while the Auxiliary (AUX) clock can optionally be used as a source for the Audio and/or Video PLLs.

The DEV and AUX clocks can be sourced in two ways:

1. Using an external crystal in conjunction with the internal oscillator or
2. Using an external 1.8-V LVCMOS-compatible clock input

Note: The external crystals used with the internal oscillators must operate in fundamental parallel resonant mode only. There is no overtone support.

The DEV Clock should in most cases be 20 MHz. However, it can optionally range anywhere from 20 - 30 MHz if the following are true:

• The DEV Clock is not used to source the SATA reference clock
• A precise 32768-Hz clock is not needed for Real-Time Clock functionality
• If the boot mode is FAST XIP

The AUX Clock is optional and can range from 20-30 MHz. AUX Clock can be used to source the Audio and/or Video PLLs when a very precise audio or video frequency is required.

6.4.1.1 Using the Internal Oscillators

When the internal oscillators are used to generate the DEV and AUX clocks, external crystals are required to be connected across the DEVOSC or AUXOSC oscillator MXI and MXO pins, along with two load capacitors (see Figure 6-7 and Figure 6-8). The external crystal load capacitors should also be connected to the associated oscillator ground pin (VSSA_DEVOSC or VSSA_AUXOSC). The capacitors should not be connected to board ground (VSS).

Figure 6-7 Device Oscillator

Figure 6-8 Auxiliary Oscillator

The load capacitors, C1 and C2 in the above pictures, should be chosen such that the below equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator MXI, MXO, and VSS pins.

Table 6-11 Input Requirements for Crystal Circuit on the Device Oscillator (DEVOSC)

PARAMETER			MIN	TYP	MAX	UNIT
	Start-up time (from power up until oscillating at stable frequency)				4	ms
	Crystal Oscillation frequency(1)		20	20	30	MHz
	Parallel Load Capacitance (C1 and C2)		12		24	pF
	Crystal ESR				50	Ω
	Crystal Shunt Capacitance				5	pF
	Crystal Oscillation Mode		Fundamental Only			n/a
	Crystal Frequency Stability	If Ethernet not used			±200	ppm
		If MII is used and RGMII, RMII not used			±100
		If RGMII, or RMII used			±50

(1) 20-MHz DEV clock is required for all bootmodes other than Fast XIP. For more detailed information on boot modes, see the ROM Code Memory and Peripheral Booting chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

Table 6-12 Input Requirements for Crystal Circuit on the Auxiliary Oscillator (AUXOSC)

PARAMETER		MIN	MAX	UNIT
	Start-up time (from power up until oscillating at stable frequency)		4	ms
	Crystal Oscillation frequency	20	30	MHz
	Parallel Load Capacitance (C1 and C2)	12	24	pF
	Crystal ESR		50	Ω
	Crystal Shunt Capacitance		5	pF
	Crystal Oscillation Mode	Fundamental Only		n/a
	Crystal Frequency stability(1)		±50	ppm

(1) Applies only when sourcing the HDMI or HDVPSS DAC clocks from the AUXOSC

6.4.1.2 Using a 1.8V LVCMOS-Compatible Clock Input

A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillators as the DEV and AUX clock inputs to the system. The external connections to support this are shown in Figure 6-9 and Figure 6-10. The DEV_CLKIN and AUX_CLKIN pins are connected to the 1.8-V LVCMOS-Compatible clock sources. The DEV_MXO and AUX_MXO pins are left unconnected. The VSSA_DEVOSC and VSSA_AUXOSC pins are connected to board ground (VSS).

Figure 6-9 1.8-V LVCMOS-Compatible Clock Input (DEV_OSC)

Figure 6-10 1.8-V LVCMOS-Compatible Clock Input (AUX_OSC)

The clock source must meet the DEVOSC_MXI/DEV_CLKIN timing requirements shown in Table 6-15, Timing Requirements for DEVOSC_MXI/DEV_CLKIN.

The clock source must meet the AUXOSC_MXI/AUX_CLKIN timing requirements shown in Table 6-16, Timing Requirements for AUXOSC_MXI/AUX_CLKIN.

6.4.2 SERDES_CLKN/P Input Clock

A high-quality, low-jitter differential clock source is required for the PCIE PHY and is an optional clock source for the SATA PHY. The clock is required to be AC coupled to the SERDES_CLKP and SERDES_CLKN device pins according to the specifications in Table 6-13. Both the clock source and the coupling capacitors should be placed physically as close to the processor as possible. In addition, make sure to follow any PCB routing and termination recommendations that the clock source manufacturer recommends.

The differential clock source is required to meet the REFCLK AC Specifications outlined in the PCI-EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0, at the input to the AC coupling capacitors.

In addition, LVDS clock sources that are compliant to the above specification, but with the following exceptions, are also acceptable:

6.4.3 AUD_CLKINx Input Clocks

External clock inputs can optionally be provided at the AUD_CLKIN0/1/2 pins to serve as a reference clocks for the following modules:

• McASP3/4/5
• McBSP
• TIMER1/2/3/4/5/6/7/8

6.4.4 CLKIN32 Input Clock

An external 32768-Hz clock input can optionally be provided at the CLKIN32 pin to serve as a reference clock in place of the RTCDIVIDER clock for the following Modules:

• RTC
• GPIO0/1/2/3
• TIMER1/2/3/4/5/6/7/8
• ARM Cortex-A8
• SYNCTIMER

The CLKIN32 source must meet the timing requirements shown in Table 6-18.

6.4.5 External Input Clocks

There are three pins referred to as AUD_CLKIN0,1,2 which are used as optional sources for HDMI I2S, McASP, McBSP and TIMER1-8. The maximum IO pin frequency for these three input clocks is 50MHz.

6.4.6 Output Clocks Select Logic

The device includes two selectable general-purpose clock outputs (CLKOUT0 and CLKOUT1). The source for these output clocks is controlled by the CLKOUT_MUX register in the Control Module (see Figure 6-11).

A. Muxed output of DEVOSC clock, USBPLL clock output, VIDEO0 PLL Clock output, and RTC DIVIDER output.

Figure 6-11 CLKOUTx Source Selection Logic

For detailed information on the CLKOUTx switching characteristics, see Table 6-19.

6.4.7 Input/Output Clocks Electrical Data/Timing

Note: If an external clock oscillator is used, a single clean power supply should be used to power both the device and the external clock oscillator circuit.

Figure 6-12 DEV_MXI/DEV_CLKIN Timing

Figure 6-13 AUX_MXI/AUX_CLKIN Timing

Figure 6-14 AUD_CLKINx Timing

Figure 6-15 CLKIN32 Timing

Figure 6-16 CLKOUTx Timing

6.4.8 PLLs

The device contains 12 top-level PLLs, and 4 embedded PLLs (within the ARM Cortex-A8, PCIE, SATA, and CSI) that provide clocks to different parts of the system. Figure 6-17 and Figure 6-18 show simplified block diagrams of the Top-Level PLL and PLL_ARM. In addition, see the System Clocking Overview (Figure 6-6) for a high-level view of the device clock architecture including the PLL reference clock sources and connections.

Figure 6-17 Top-Level PLL Simplified Block Diagram

Figure 6-18 PLL_ARM Simplified Block Diagram

The reference clock for most of the PLLs comes from the DEV input clock, with select PLLs also having the option to use the AUX input clock as a reference. Also, each PLL supports a Bypass mode in which the reference clock can be directly passed to the PLL CLKOUT through a divider. All device PLL’s will come-up in Bypass mode after reset.

For details on programming the device PLLs, see the Control Module chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).

6.4.9 SYSCLKs

In some cases, the system clock inputs and PLL outputs are sent to the PRCM Module for division and multiplexing before being routed to the various device Modules. These clock outputs from the PRCM Module are called SYSCLKs. Table Table 6-26 lists the device SYSCLKs along with their maximum supported clock frequencies. In addition, limits shown in these tables may be further restricted by the clock frequency limitations of the device modules using these clocks. For more details on Module Clock frequency limits, see Section 6.4.10 Module Clocks.

6.4.10 Module Clocks

Device Modules either receive their clock directly from an external clock input, directly from a PLL, or from a PRCM SYSCLK output. Table 6-27 lists the clock source options for each Module on this device, along with the maximum frequency that Module can accept. To ensure proper Module functionality, the device PLLs and dividers must be programmed not to exceed the maximum frequencies listed in this table.

6.5.1 ARM Cortex-A8 Interrupts

The ARM Cortex-A8 Interrupt Controller (AINTC) is responsible for prioritizing all service requests from the System peripherals and generating either IRQs or FIQs to the Cortex-A8. The AINTC has the capability to handle up to 128 requests, and the priority of the interrupt inputs are programmable. Table 6-28 lists the interrupt sources for the AINTC.

Note: For General-Purpose devices, the AINTC does not support the generation of FIQs to the ARM processor.

For more details on ARM Cortex-A8 interrupt control, see the ARM Interrupt Controller (AINTC) chapter of the AM387x Sitara™ ARM Processors Technical Reference Manual (SPRUGZ7).