5.12.8.2.1.3.3 DDR3 PCB Stackup
The minimum stackup for routing the DDR3 interface is a four-layer stack up as shown in Table 5-51. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.
Table 5-51 Minimum PCB Stackup(1)
LAYER |
TYPE |
DESCRIPTION |
1 |
Signal |
Top signal routing |
2 |
Plane |
Ground |
3 |
Plane |
Split Power Plane |
4 |
Signal |
Bottom signal routing |
- All signals that have critical signal integrity requirements should be routed first on layer 1. It may not be possible to route all of these signals on layer 1 which requires some to be routed on layer 4. When this is done, the signal routes on layer 4 should not cross splits in the power plane.
Table 5-52 PCB Stackup Specifications(1)
NO. |
PARAMETER |
MIN |
TYP |
MAX |
UNIT |
1 |
PCB routing and plane layers |
4 |
|
|
|
2 |
Signal routing layers |
2 |
|
|
|
3 |
Full ground reference layers under DDR3 routing region(2) |
1 |
|
|
|
4 |
Full VDDS_DDR power reference layers under the DDR3 routing region(2) |
1 |
|
|
|
5 |
Number of reference plane cuts allowed within DDR3 routing region(3) |
|
|
0 |
|
6 |
Number of layers between DDR3 routing layer and reference plane(4) |
|
|
0 |
|
7 |
PCB routing feature size |
|
4 |
|
mils |
8 |
PCB trace width, w |
|
4 |
|
mils |
9 |
PCB BGA escape via pad size(5) |
|
18 |
20 |
mils |
10 |
PCB BGA escape via hole size |
|
10 |
|
mils |
13 |
Single-ended impedance, Zo(6) |
|
50 |
75 |
Ω |
14 |
Impedance control(7)(8) |
Zo-5 |
Zo |
Zo+5 |
Ω |
- For the DDR3 device BGA pad size, see the DDR3 device manufacturer documentation.
- Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer return current as the trace routes switch routing layers.
- No traces should cross reference plane cuts within the DDR3 routing region. High-speed signal traces crossing reference plane cuts create large return current paths which can lead to excessive crosstalk and EMI radiation.
- Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.
- An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available for power routing. An 18-mil pad is required for minimum layer count escape.
- Zo is the nominal singled-ended impedance selected for the PCB.
- This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen Zo defined by the single-ended impedance parameter.
- Tighter impedance control is required to ensure flight time skew is minimal.