SPRS851E June   2014  – January 2019 AM4372 , AM4376 , AM4377 , AM4378 , AM4379

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
      1. Table 4-1 ZDN Ball Map [Section Top Left - Top View]
      2. Table 4-2 ZDN Ball Map [Section Top Middle - Top View]
      3. Table 4-3 ZDN Ball Map [Section Top Right - Top View]
      4. Table 4-4 ZDN Ball Map [Section Middle Left - Top View]
      5. Table 4-5 ZDN Ball Map [Section Middle Middle - Top View]
      6. Table 4-6 ZDN Ball Map [Section Middle Right - Top View]
      7. Table 4-7 ZDN Ball Map [Section Bottom Left - Top View]
      8. Table 4-8 ZDN Ball Map [Section Bottom Middle - Top View]
      9. Table 4-9 ZDN Ball Map [Section Bottom Right - Top View]
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  ADC Interfaces
      2. 4.3.2  CAN Interfaces
      3. 4.3.3  Camera (VPFE) Interfaces
      4. 4.3.4  Debug Subsystem Interface
      5. 4.3.5  Display Subsystem (DSS) Interface
      6. 4.3.6  Ethernet (GEMAC_CPSW) Interfaces
      7. 4.3.7  External Memory Interfaces
      8. 4.3.8  General Purpose IOs
      9. 4.3.9  HDQ Interface
      10. 4.3.10 I2C Interfaces
      11. 4.3.11 McASP Interfaces
      12. 4.3.12 Miscellaneous
      13. 4.3.13 PRU-ICSS0 Interface
      14. 4.3.14 PRU-ICSS1 Interface
      15. 4.3.15 QSPI Interface
      16. 4.3.16 RTC Subsystem Interface
      17. 4.3.17 Removable Media Interfaces
      18. 4.3.18 SPI Interfaces
      19. 4.3.19 Timer Interfaces
      20. 4.3.20 UART Interfaces
      21. 4.3.21 USB Interfaces
      22. 4.3.22 eCAP Interfaces
      23. 4.3.23 eHRPWM Interfaces
      24. 4.3.24 eQEP Interfaces
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Operating Performance Points
    5. 5.5  Recommended Operating Conditions
    6. 5.6  Power Consumption Summary
    7. 5.7  DC Electrical Characteristics
    8. 5.8  ADC0: Touch Screen Controller and Analog-to-Digital Subsystem Electrical Parameters
    9. 5.9  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-6 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.9.1     Hardware Requirements
      3. 5.9.2     Programming Sequence
      4. 5.9.3     Impact to Your Hardware Warranty
    10. 5.10 Thermal Resistance Characteristics
      1. Table 5-7 Thermal Resistance Characteristics (NFBGA Package) [ZDN]
    11. 5.11 External Capacitors
      1. 5.11.1 Voltage Decoupling Capacitors
        1. 5.11.1.1 Core Voltage Decoupling Capacitors
        2. 5.11.1.2 IO and Analog Voltage Decoupling Capacitors
      2. 5.11.2 Output Capacitors
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. 5.12.1.1 Power Supply Slew Rate Requirement
        2. 5.12.1.2 Power-Up Sequencing
        3. 5.12.1.3 Power-Down Sequencing
      2. 5.12.2  Clock
        1. 5.12.2.1 PLLs
          1. 5.12.2.1.1 Digital Phase-Locked Loop Power Supply Requirements
        2. 5.12.2.2 Input Clock Specifications
        3. 5.12.2.3 Input Clock Requirements
          1. 5.12.2.3.1 OSC0 Internal Oscillator Clock Source
            1. Table 5-12 OSC0 Crystal Circuit Requirements
            2. Table 5-13 OSC0 Crystal Circuit Characteristics
          2. 5.12.2.3.2 OSC0 LVCMOS Digital Clock Source
          3. 5.12.2.3.3 OSC1 Internal Oscillator Clock Source
            1. Table 5-15 OSC1 Crystal Circuit Requirements
            2. Table 5-16 OSC1 Crystal Circuit Characteristics
          4. 5.12.2.3.4 OSC1 LVCMOS Digital Clock Source
          5. 5.12.2.3.5 OSC1 Not Used
        4. 5.12.2.4 Output Clock Specifications
        5. 5.12.2.5 Output Clock Characteristics
          1. 5.12.2.5.1 CLKOUT1
          2. 5.12.2.5.2 CLKOUT2
      3. 5.12.3  Timing Parameters and Board Routing Analysis
      4. 5.12.4  Recommended Clock and Control Signal Transition Behavior
      5. 5.12.5  Controller Area Network (CAN)
        1. 5.12.5.1 DCAN Electrical Data and Timing
          1. Table 5-18 Timing Requirements for DCANx Receive
          2. Table 5-19 Switching Characteristics for DCANx Transmit
      6. 5.12.6  DMTimer
        1. 5.12.6.1 DMTimer Electrical Data and Timing
          1. Table 5-20 Timing Requirements for DMTimer [1-11]
          2. Table 5-21 Switching Characteristics for DMTimer [4-7]
      7. 5.12.7  Ethernet Media Access Controller (EMAC) and Switch
        1. 5.12.7.1 Ethernet MAC and Switch Electrical Data and Timing
          1. Table 5-22 Ethernet MAC and Switch Timing Conditions
          2. 5.12.7.1.1 Ethernet MAC/Switch MDIO Electrical Data and Timing
            1. Table 5-23 Timing Requirements for MDIO_DATA
            2. Table 5-24 Switching Characteristics for MDIO_CLK
            3. Table 5-25 MDIO Switching Characteristics - MDIO_DATA
          3. 5.12.7.1.2 Ethernet MAC and Switch MII Electrical Data and Timing
            1. Table 5-26 Timing Requirements for GMII[x]_RXCLK - MII Mode
            2. Table 5-27 Timing Requirements for GMII[x]_TXCLK - MII Mode
            3. Table 5-28 Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode
            4. Table 5-29 Switching Characteristics for GMII[x]_TXD[3:0], and GMII[x]_TXEN - MII Mode
          4. 5.12.7.1.3 Ethernet MAC and Switch RMII Electrical Data and Timing
            1. Table 5-30 Timing Requirements for RMII[x]_REFCLK - RMII Mode
            2. Table 5-31 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
            3. Table 5-32 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
          5. 5.12.7.1.4 Ethernet MAC and Switch RGMII Electrical Data and Timing
            1. Table 5-33 Timing Requirements for RGMII[x]_RCLK - RGMII Mode
            2. Table 5-34 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
            3. Table 5-35 Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
            4. Table 5-36 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
      8. 5.12.8  External Memory Interfaces
        1. 5.12.8.1 General-Purpose Memory Controller (GPMC)
          1. 5.12.8.1.1 GPMC and NOR Flash—Synchronous Mode
            1. Table 5-37 GPMC and NOR Flash Timing Conditions—Synchronous Mode
            2. Table 5-38 GPMC and NOR Flash Timing Requirements—Synchronous Mode
            3. Table 5-39 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
          2. 5.12.8.1.2 GPMC and NOR Flash—Asynchronous Mode
            1. Table 5-40 GPMC and NOR Flash Timing Conditions—Asynchronous Mode
            2. Table 5-41 GPMC and NOR Flash Internal Timing Parameters—Asynchronous Mode
            3. Table 5-42 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
            4. Table 5-43 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
          3. 5.12.8.1.3 GPMC and NAND Flash—Asynchronous Mode
            1. Table 5-44 GPMC and NAND Flash Timing Conditions—Asynchronous Mode
            2. Table 5-45 GPMC and NAND Flash Internal Timing Parameters—Asynchronous Mode
            3. Table 5-46 GPMC and NAND Flash Timing Requirements—Asynchronous Mode
            4. Table 5-47 GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
        2. 5.12.8.2 Memory Interface
          1. 5.12.8.2.1 DDR3 and DDR3L Routing Guidelines
            1. 5.12.8.2.1.1 Board Designs
            2. 5.12.8.2.1.2 DDR3 Device Combinations
            3. 5.12.8.2.1.3 DDR3 Interface
              1. 5.12.8.2.1.3.1  DDR3 Interface Schematic
              2. 5.12.8.2.1.3.2  Compatible JEDEC DDR3 Devices
              3. 5.12.8.2.1.3.3  DDR3 PCB Stackup
              4. 5.12.8.2.1.3.4  DDR3 Placement
              5. 5.12.8.2.1.3.5  DDR3 Keepout Region
              6. 5.12.8.2.1.3.6  DDR3 Bulk Bypass Capacitors
              7. 5.12.8.2.1.3.7  DDR3 High-Speed Bypass Capacitors
                1. 5.12.8.2.1.3.7.1 Return Current Bypass Capacitors
              8. 5.12.8.2.1.3.8  DDR3 Net Classes
              9. 5.12.8.2.1.3.9  DDR3 Signal Termination
              10. 5.12.8.2.1.3.10 DDR3 DDR_VREF Routing
              11. 5.12.8.2.1.3.11 DDR3 VTT
            4. 5.12.8.2.1.4 DDR3 CK and ADDR_CTRL Topologies and Routing Definition
              1. 5.12.8.2.1.4.1 Using Two DDR3 Devices (x8 or x16)
                1. 5.12.8.2.1.4.1.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
                2. 5.12.8.2.1.4.1.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
              2. 5.12.8.2.1.4.2 Using Four 8-Bit DDR3 Devices
                1. 5.12.8.2.1.4.2.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
                2. 5.12.8.2.1.4.2.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
              3. 5.12.8.2.1.4.3 One 16-Bit DDR3 Device
                1. 5.12.8.2.1.4.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
                2. 5.12.8.2.1.4.3.2 CK and ADDR_CTRL Routing, One DDR3 Device
            5. 5.12.8.2.1.5 Data Topologies and Routing Definition
              1. 5.12.8.2.1.5.1 DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices
              2. 5.12.8.2.1.5.2 DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices
            6. 5.12.8.2.1.6 Routing Specification
              1. 5.12.8.2.1.6.1 CK and ADDR_CTRL Routing Specification
              2. 5.12.8.2.1.6.2 DQS[x] and DQ[x] Routing Specification
          2. 5.12.8.2.2 LPDDR2 Routing Guidelines
            1. 5.12.8.2.2.1 LPDDR2 Board Designs
            2. 5.12.8.2.2.2 LPDDR2 Device Configurations
            3. 5.12.8.2.2.3 LPDDR2 Interface
              1. 5.12.8.2.2.3.1 LPDDR2 Interface Schematic
              2. 5.12.8.2.2.3.2 Compatible JEDEC LPDDR2 Devices
              3. 5.12.8.2.2.3.3 LPDDR2 PCB Stackup
              4. 5.12.8.2.2.3.4 LPDDR2 Placement
              5. 5.12.8.2.2.3.5 LPDDR2 Keepout Region
              6. 5.12.8.2.2.3.6 LPDDR2 Net Classes
              7. 5.12.8.2.2.3.7 LPDDR2 Signal Termination
              8. 5.12.8.2.2.3.8 LPDDR2 DDR_VREF Routing
            4. 5.12.8.2.2.4 Routing Specification
              1. 5.12.8.2.2.4.1 DQS[x] and DQ[x] Routing Specification
              2. 5.12.8.2.2.4.2 CK and ADDR_CTRL Routing Specification
      9. 5.12.9  Display Subsystem (DSS)
        1. 5.12.9.1 DSS—Parallel Interface
          1. 5.12.9.1.1 DSS—Parallel Interface—Bypass Mode
            1. 5.12.9.1.1.1 DSS—Parallel Interface—Bypass Mode—TFT Mode
            2. 5.12.9.1.1.2 DSS—Parallel Interface—Bypass Mode—STN Mode
          2. 5.12.9.1.2 DSS—Parallel Interface—RFBI Mode—Applications
            1. 5.12.9.1.2.1 DSS—Parallel Interface—RFBI Mode—MIPI DBI 2.0—LCD Panel
            2. 5.12.9.1.2.2 DSS—Parallel Interface—RFBI Mode—Pico DLP
      10. 5.12.10 Camera (VPFE)
        1. 5.12.10.1 Camera (VPFE) Timing
          1. Table 5-80 VPFE Timing Requirements
          2. Table 5-81 VPFE Output Switching Characteristics
      11. 5.12.11 Inter-Integrated Circuit (I2C)
        1. 5.12.11.1 I2C Electrical Data and Timing
          1. Table 5-82 I2C Timing Conditions - Slave Mode
          2. Table 5-83 Timing Requirements for I2C Input Timings
          3. Table 5-84 Switching Characteristics for I2C Output Timings
      12. 5.12.12 Multichannel Audio Serial Port (McASP)
        1. 5.12.12.1 McASP Device-Specific Information
        2. 5.12.12.2 McASP Electrical Data and Timing
          1. Table 5-85 McASP Timing Conditions
          2. Table 5-86 Timing Requirements for McASP
          3. Table 5-87 Switching Characteristics for McASP
      13. 5.12.13 Multichannel Serial Port Interface (McSPI)
        1. 5.12.13.1 McSPI Electrical Data and Timing
          1. 5.12.13.1.1 McSPI—Slave Mode
            1. Table 5-88 McSPI Timing Conditions—Slave Mode
            2. Table 5-89 Timing Requirements for McSPI Input Timings—Slave Mode
            3. Table 5-90 Switching Characteristics for McSPI Output Timings—Slave Mode
          2. 5.12.13.1.2 McSPI—Master Mode
            1. Table 5-91 McSPI Timing Conditions—Master Mode
            2. Table 5-92 Timing Requirements for McSPI Input Timings—Master Mode
            3. Table 5-93 Switching Characteristics for McSPI Output Timings—Master Mode
      14. 5.12.14 Quad Serial Port Interface (QSPI)
        1. Table 5-94 QSPI Switching Characteristics
      15. 5.12.15 HDQ/1-Wire Interface (HDQ/1-Wire)
        1. 5.12.15.1 HDQ Protocol
        2. 5.12.15.2 1-Wire Protocol
      16. 5.12.16 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
        1. 5.12.16.1 Programmable Real-Time Unit (PRU-ICSS PRU)
          1. Table 5-99  PRU-ICSS PRU Timing Conditions
          2. 5.12.16.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
            1. Table 5-100 PRU-ICSS PRU Timing Requirements - Direct Input Mode
            2. Table 5-101 PRU-ICSS PRU Switching Requirements - Direct Output Mode
          3. 5.12.16.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
            1. Table 5-102 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
          4. 5.12.16.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
            1. Table 5-103 PRU-ICSS PRU Timing Requirements - Shift In Mode
            2. Table 5-104 PRU-ICSS PRU Switching Requirements - Shift Out Mode
          5. 5.12.16.1.4 PRU-ICSS Sigma Delta Electrical Data and Timing
            1. Table 5-105 PRU-ICSS Timing Requirements - Sigma Delta Mode
          6. 5.12.16.1.5 PRU-ICSS ENDAT Electrical Data and Timing
            1. Table 5-106 PRU-ICSS Timing Requirements - ENDAT Mode
            2. Table 5-107 PRU-ICSS Switching Requirements - ENDAT Mode
        2. 5.12.16.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
          1. Table 5-108 PRU-ICSS ECAT Timing Conditions
          2. 5.12.16.2.1 PRU-ICSS ECAT Electrical Data and Timing
            1. Table 5-109 PRU-ICSS ECAT Timing Requirements - Input Validated With LATCH_IN
            2. Table 5-110 PRU-ICSS ECAT Timing Requirements - Input Validated With SYNCx
            3. Table 5-111 PRU-ICSS ECAT Timing Requirements - Input Validated With Start of Frame (SOF)
            4. Table 5-112 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
            5. Table 5-113 PRU-ICSS ECAT Switching Requirements - Digital IOs
        3. 5.12.16.3 PRU-ICSS MII_RT and Switch
          1. Table 5-114 PRU-ICSS MII_RT Switch Timing Conditions
          2. 5.12.16.3.1 PRU-ICSS MDIO Electrical Data and Timing
            1. Table 5-115 PRU-ICSS MDIO Timing Requirements - MDIO_DATA
            2. Table 5-116 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
            3. Table 5-117 PRU-ICSS MDIO Switching Characteristics - MDIO_DATA
          3. 5.12.16.3.2 PRU-ICSS MII_RT Electrical Data and Timing
            1. Table 5-118 PRU-ICSS MII_RT Timing Requirements - MII_RXCLK
            2. Table 5-119 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
            3. Table 5-120 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
            4. Table 5-121 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
        4. 5.12.16.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
          1. Table 5-122 Timing Requirements for PRU-ICSS UART Receive
          2. Table 5-123 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
      17. 5.12.17 Multimedia Card (MMC) Interface
        1. 5.12.17.1 MMC Electrical Data and Timing
          1. Table 5-124 MMC Timing Conditions
          2. Table 5-125 Timing Requirements for MMC[0]_CMD and MMC[0]_DAT[7:0]
          3. Table 5-126 Timing Requirements for MMC[1/2]_CMD and MMC[1/2]_DAT[7:0]
          4. Table 5-127 Switching Characteristics for MMC[x]_CLK
          5. Table 5-128 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—HSPE=0
          6. Table 5-129 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—HSPE=1
      18. 5.12.18 Universal Asynchronous Receiver/Transmitter (UART)
        1. 5.12.18.1 UART Electrical Data and Timing
          1. Table 5-130 Timing Requirements for UARTx Receive
          2. Table 5-131 for UARTx Transmit
        2. 5.12.18.2 UART IrDA Interface
    13. 5.13 Emulation and Debug
      1. 5.13.1 IEEE 1149.1 JTAG
        1. 5.13.1.1 JTAG Electrical Data and Timing
          1. Table 5-134 Timing Requirements for JTAG
          2. Table 5-135 Switching Characteristics for JTAG
  6. 6Device and Documentation Support
    1. 6.1 Device Nomenclature
    2. 6.2 Tools and Software
    3. 6.3 Documentation Support
    4. 6.4 Related Links
    5. 6.5 Community Resources
    6. 6.6 Trademarks
    7. 6.7 Electrostatic Discharge Caution
    8. 6.8 Glossary
  7. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 Via Channel
    2. 7.2 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZDN|491
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.12.8.2.1.6.1 CK and ADDR_CTRL Routing Specification

Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. A metric to establish this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the length between the points when connecting them only with horizontal or vertical segments. A reasonable trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address Control Longest Manhattan distance.

Given the clock and address pin locations on the device and the DDR3 memories, the maximum possible Manhattan distance can be determined given the placement. Figure 5-76 shows this distance for two loads. It is from this distance that the specifications on the lengths of the transmission lines for the address bus are determined. CACLM is determined similarly for other address bus configurations; that is, it is based on the longest net of the CK and ADDR_CTRL net class. For CK and ADDR_CTRL routing, these specifications are contained in Table 5-58.

AM4372 AM4376 AM4377 AM4378 AM4379 caclm_2_4_addr_sprs851.gif
A. It is very likely that the longest CK and ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3 memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that satisfies this criteria and use as the baseline for CK and ADDR_CTRL skew matching and length control.

The length of shorter CK and ADDR_CTRL stubs as well as the length of the terminator stub are not included in this length calculation. Nonincluded lengths are grayed out in the figure.

Assuming A8 is the longest, CACLM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.
Figure 5-76 CACLM for Two or Four Address Loads on One Side of PCB

Table 5-58 CK and ADDR_CTRL Routing Specification(1)(2)(3)

NO. PARAMETER MIN TYP MAX UNIT
1 A1+A2 length 2500 mils
2 A1+A2 skew 25 mils
3 A3 length 660 mils
4 A3 skew(4) 25 mils
5 A3 skew(5) 125 mils
6 A4 length 660 mils
7 A4 skew 25 mils
8 AS length 100 mils
9 AS skew 25 mils
10 AS+ and AS- length 70 mils
11 AS+ and AS- skew 5 mils
12 AT length(6) 500 mils
13 AT skew(7) 100 mils
14 AT skew(8) 5 mils
15 CK and ADDR_CTRL nominal trace length(9) CACLM-50 CACLM CACLM+50 mils
16 Center-to-center CK to other DDR3 trace spacing(10) 4 w
17 Center-to-center ADDR_CTRL to other DDR3 trace spacing(10)(11) 4 w
18 Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(10) 3 w
19 CK center-to-center spacing(12)
20 CK spacing to other net(10) 4 w
21 Rcp(13) Zo-1 Zo Zo+1 Ω
22 Rtt(13)(14) Zo-5 Zo Zo+5 Ω
  1. CK represents the clock net class, and ADDR_CTRL represents the address and control signal net class.
  2. The use of vias should be minimized.
  3. Additional bypass capacitors are required when using the VDDS_DDR plane as the reference plane to allow the return current to jump between the VDDS_DDR plane and the ground plane when the net class switches layers at a via.
  4. Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).
  5. Nonmirrored configuration (all DDR3 memories on same side of PCB).
  6. While this length can be increased for convenience, its length should be minimized.
  7. ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.
  8. CK net class only.
  9. CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes + 300 mils. For definition, see Section 5.12.8.2.1.6.1 and Figure 5-76.
  10. Center-to-center spacing is allowed to fall to minimum (w) for up to 1250 mils of routed length.
  11. Signals from one DQ net class should be considered other DDR3 traces to another DQ net class.
  12. CK spacing set to ensure proper differential impedance. Differential impedance should be Zo x 2, where Zo is the single-ended impedance defined in Table 5-52.
  13. Source termination (series resistor at driver) is specifically not allowed.
  14. Termination values should be uniform across the net class.