SPRS982H December   2016  – December 2019 AM5746 , AM5748 , AM5749

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  EMIF
      5. 4.3.5  GPMC
      6. 4.3.6  Timer
      7. 4.3.7  I2C
      8. 4.3.8  HDQ1W
      9. 4.3.9  UART
      10. 4.3.10 McSPI
      11. 4.3.11 QSPI
      12. 4.3.12 McASP
      13. 4.3.13 USB
      14. 4.3.14 SATA
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN and MCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 MLB
      19. 4.3.19 eMMC/SD/SDIO
      20. 4.3.20 GPIO
      21. 4.3.21 KBD
      22. 4.3.22 PWM
      23. 4.3.23 PRU-ICSS
      24. 4.3.24 Test Interfaces
      25. 4.3.25 System and Miscellaneous
        1. 4.3.25.1 Sysboot
        2. 4.3.25.2 PRCM
        3. 4.3.25.3 RTCSS
        4. 4.3.25.4 SDMA
        5. 4.3.25.5 INTC
        6. 4.3.25.6 Observability
        7. 4.3.25.7 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH) Limits
      1. Table 5-1 Power-On Hours (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-7  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-8  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-9  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-10 IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-11 LVCMOS OSC Buffers DC Electrical Characteristics
      6. Table 5-12 BC1833IHHV Buffers DC Electrical Characteristics
      7. Table 5-13 Dual Voltage SDIO1833 DC Electrical Characteristics
      8. Table 5-14 Dual Voltage LVCMOS DC Electrical Characteristics
      9. 5.7.1      HDMIPHY DC Electrical Characteristics
      10. 5.7.2      USBPHY DC Electrical Characteristics
      11. 5.7.3      SATAPHY DC Electrical Characteristics
      12. 5.7.4      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-15 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Characteristics
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8V and 3.3V Signal Transition Levels
          2. 5.10.1.1.2 1.8V and 3.3V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
          4. 5.10.4.1.4 RTC Oscillator Input Clock
            1. 5.10.4.1.4.1 RTC Oscillator External Crystal
            2. 5.10.4.1.4.2 RTC Oscillator Input Clock
        2. 5.10.4.2 RC On-die Oscillator Clock
        3. 5.10.4.3 Output Clocks
        4. 5.10.4.4 DPLLs, DLLs
          1. 5.10.4.4.1 DPLL Characteristics
          2. 5.10.4.4.2 DLL Characteristics
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  EMIF
        7. 5.10.6.7  GPMC
          1. 5.10.6.7.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.7.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.7.3 GPMC/NAND Flash Interface Asynchronous Timing
        8. 5.10.6.8  I2C
          1. Table 5-65 Timing Requirements for I2C Input Timings
          2. Table 5-66 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
          3. Table 5-67 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        9. 5.10.6.9  HDQ1W
          1. 5.10.6.9.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.9.2 HDQ/1-Wire—1-Wire Mode
        10. 5.10.6.10 UART
          1. Table 5-72 Timing Requirements for UART
          2. Table 5-73 Switching Characteristics Over Recommended Operating Conditions for UART
        11. 5.10.6.11 McSPI
        12. 5.10.6.12 QSPI
        13. 5.10.6.13 McASP
          1. Table 5-80 Timing Requirements for McASP1
          2. Table 5-81 Timing Requirements for McASP2
          3. Table 5-82 Timing Requirements for McASP3/4/5/6/7/8
          4. Table 5-83 Switching Characteristics Over Recommended Operating Conditions for McASP1
          5. Table 5-84 Switching Characteristics Over Recommended Operating Conditions for McASP2
          6. Table 5-85 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
        14. 5.10.6.14 USB
          1. 5.10.6.14.1 USB1 DRD PHY
          2. 5.10.6.14.2 USB2 PHY
        15. 5.10.6.15 SATA
        16. 5.10.6.16 PCIe
        17. 5.10.6.17 CAN
          1. 5.10.6.17.1 DCAN
          2. 5.10.6.17.2 MCAN-FD
          3. Table 5-97  Timing Requirements for CANx Receive
          4. Table 5-98  Switching Characteristics Over Recommended Operating Conditions for CANx Transmit
        18. 5.10.6.18 GMAC_SW
          1. 5.10.6.18.1 GMAC MII Timings
            1. Table 5-99  Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-100 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-101 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-102 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.18.2 GMAC MDIO Interface Timings
          3. 5.10.6.18.3 GMAC RMII Timings
            1. Table 5-107 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-108 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-109 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-110 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.18.4 GMAC RGMII Timings
            1. Table 5-114 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-115 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-116 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-117 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        19. 5.10.6.19 eMMC/SD/SDIO
          1. 5.10.6.19.1 MMC1—SD Card Interface
            1. 5.10.6.19.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.19.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.19.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.19.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.19.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.19.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.19.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.19.2 MMC2 — eMMC
            1. 5.10.6.19.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.19.2.2 High Speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.19.2.3 High Speed HS200 JC64 SDR, 8-bit data, half cycle
            4. 5.10.6.19.2.4 High Speed JC64 DDR, 8-bit data
          3. 5.10.6.19.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.19.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.19.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.19.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.19.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.19.3.5 MMC3 SDIO High Speed UHS-I SDR50 Mode, Half Cycle
        20. 5.10.6.20 PRU-ICSS
          1. 5.10.6.20.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.10.6.20.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-166 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-167 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.10.6.20.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-168 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            3. 5.10.6.20.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-169 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-170 PRU-ICSS PRU Switching Requirements - Shift Out Mode
            4. 5.10.6.20.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
              1. Table 5-171 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-172 PRU-ICSS PRU Timing Requirements - EnDAT Mode
              3. Table 5-173 PRU-ICSS PRU Switching Requirements - EnDAT Mode
          2. 5.10.6.20.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.10.6.20.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-174 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
              2. Table 5-175 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              3. Table 5-176 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
              4. Table 5-177 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
              5. Table 5-178 PRU-ICSS ECAT Switching Requirements - Digital IOs
          3. 5.10.6.20.3 PRU-ICSS MII_RT and Switch
            1. 5.10.6.20.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-179 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-180 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
              3. Table 5-181 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.10.6.20.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-182 PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
              2. Table 5-183 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
              3. Table 5-184 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-185 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
          4. 5.10.6.20.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-186 Timing Requirements for PRU-ICSS UART Receive
            2. Table 5-187 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.10.6.20.5 PRU-ICSS IOSETs
          6. 5.10.6.20.6 PRU-ICSS Manual Functional Mapping
        21. 5.10.6.21 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 JTAG
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-210 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-211 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-212 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-213 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 TPIU
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Processor Subsystems
      1. 6.2.1 MPU
      2. 6.2.2 DSP Subsystem
      3. 6.2.3 IPU
      4. 6.2.4 Interrupt Controller
      5. 6.2.5 VPE
    3. 6.3 Accelerators and Coprocessors
      1. 6.3.1 IVA
      2. 6.3.2 GPU
      3. 6.3.3 PRU-ICSS
      4. 6.3.4 EVE
    4. 6.4 Other Subsystems
      1. 6.4.1 Memory Subsystem
        1. 6.4.1.1 EMIF
        2. 6.4.1.2 GPMC
        3. 6.4.1.3 ELM
        4. 6.4.1.4 OCMC
        5. 6.4.1.5 Interprocessor Communication
          1. 6.4.1.5.1 Mailbox
          2. 6.4.1.5.2 Spinlock
      2. 6.4.2 EDMA
      3. 6.4.3 Peripherals
        1. 6.4.3.1  VIP
        2. 6.4.3.2  DSS
        3. 6.4.3.3  Timers
        4. 6.4.3.4  I2C
        5. 6.4.3.5  HDQ1W
        6. 6.4.3.6  UART
          1. 6.4.3.6.1 UART Features
          2. 6.4.3.6.2 IrDA Features
          3. 6.4.3.6.3 CIR Features
        7. 6.4.3.7  McSPI
        8. 6.4.3.8  QSPI
        9. 6.4.3.9  McASP
        10. 6.4.3.10 USB
        11. 6.4.3.11 SATA
        12. 6.4.3.12 PCIe
        13. 6.4.3.13 CAN
          1. 6.4.3.13.1 DCAN
          2. 6.4.3.13.2 MCAN-FD
        14. 6.4.3.14 GMAC_SW
        15. 6.4.3.15 eMMC/SD/SDIO
        16. 6.4.3.16 GPIO
        17. 6.4.3.17 ePWM
        18. 6.4.3.18 eCAP
        19. 6.4.3.19 eQEP
      4. 6.4.4 On-Chip Debug
    5. 6.5 Identification
      1. 6.5.1 Revision Identification
      2. 6.5.2 Die Identification
      3. 6.5.3 JTAG Identification
      4. 6.5.4 ROM Code Identification
    6. 6.6 Boot Modes
      1. 6.6.1 Boot Mode List
      2. 6.6.2 Boot Mode Pin Usage
        1. 6.6.2.1 GPMC Configuration for XIP/NAND
        2. 6.6.2.2 System Clock Speed Selection
        3. 6.6.2.3 QSPI Redundant SBL Images Offset
      3. 6.6.3 Boot Mode Selection
        1. 6.6.3.1 Booting Device Order Selection
  7. 7Applications, Implementation, and Layout
    1. 7.1 Power Supply Mapping
    2. 7.2 DDR3 Board Design and Layout Guidelines
      1. 7.2.1 DDR3 General Board Layout Guidelines
      2. 7.2.2 DDR3 Board Design and Layout Guidelines
        1. 7.2.2.1  Board Designs
        2. 7.2.2.2  DDR3 EMIFs
        3. 7.2.2.3  DDR3 Device Combinations
        4. 7.2.2.4  DDR3 Interface Schematic
          1. 7.2.2.4.1 32-Bit DDR3 Interface
          2. 7.2.2.4.2 16-Bit DDR3 Interface
        5. 7.2.2.5  Compatible JEDEC DDR3 Devices
        6. 7.2.2.6  PCB Stackup
        7. 7.2.2.7  Placement
        8. 7.2.2.8  DDR3 Keepout Region
        9. 7.2.2.9  Bulk Bypass Capacitors
        10. 7.2.2.10 High Speed Bypass Capacitors
          1. 7.2.2.10.1 Return Current Bypass Capacitors
        11. 7.2.2.11 Net Classes
        12. 7.2.2.12 DDR3 Signal Termination
        13. 7.2.2.13 VREF_DDR Routing
        14. 7.2.2.14 VTT
        15. 7.2.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.2.2.15.1 Four DDR3 Devices
            1. 7.2.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.2.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.2.2.15.2 Two DDR3 Devices
            1. 7.2.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.2.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.2.2.15.3 One DDR3 Device
            1. 7.2.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.2.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.2.2.16 Data Topologies and Routing Definition
          1. 7.2.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.2.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.2.2.17 Routing Specification
          1. 7.2.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.2.2.17.2 DQS and DQ Routing Specification
    3. 7.3 High Speed Differential Signal Routing Guidance
    4. 7.4 Power Distribution Network Implementation Guidance
    5. 7.5 Thermal Solution Guidance
    6. 7.6 Single-Ended Interfaces
      1. 7.6.1 General Routing Guidelines
      2. 7.6.2 QSPI Board Design and Layout Guidelines
    7. 7.7 LJCB_REFN/P Connections
    8. 7.8 Clock Routing Guidelines
      1. 7.8.1 32-kHz Oscillator Routing
      2. 7.8.2 Oscillator Ground Connection
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABZ|760
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.3.23 PRU-ICSS

CAUTION

The I/O timings provided in Section 5.10, Timing Requirements and Switching Characteristics are valid only if signals within a single IOSET are used. The IOSETs are defined in the Table 5-188 and Table 5-189.

NOTE

For more information, see the Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem section in the device TRM.

Table 4-24 PRU-ICSS Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL BOTTOM
PRU-ICSS 1
pr1_pru0_gpo0 PRU0 General-Purpose Output O AH6
pr1_pru0_gpo1 PRU0 General-Purpose Output O AH3
pr1_pru0_gpo2 PRU0 General-Purpose Output O AH5
pr1_pru0_gpo3 PRU0 General-Purpose Output O AG6
pr1_pru0_gpo4 PRU0 General-Purpose Output O AH4
pr1_pru0_gpo5 PRU0 General-Purpose Output O AG4
pr1_pru0_gpo6 PRU0 General-Purpose Output O AG2
pr1_pru0_gpo7 PRU0 General-Purpose Output O AG3
pr1_pru0_gpo8 PRU0 General-Purpose Output O AG5
pr1_pru0_gpo9 PRU0 General-Purpose Output O AF2
pr1_pru0_gpo10 PRU0 General-Purpose Output O AF6
pr1_pru0_gpo11 PRU0 General-Purpose Output O AF3
pr1_pru0_gpo12 PRU0 General-Purpose Output O AF4
pr1_pru0_gpo13 PRU0 General-Purpose Output O AF1
pr1_pru0_gpo14 PRU0 General-Purpose Output O AE3
pr1_pru0_gpo15 PRU0 General-Purpose Output O AE5
pr1_pru0_gpo16 PRU0 General-Purpose Output O AE1
pr1_pru0_gpo17 PRU0 General-Purpose Output O AE2
pr1_pru0_gpo18 PRU0 General-Purpose Output O AE6
pr1_pru0_gpo19 PRU0 General-Purpose Output O AD2
pr1_pru0_gpo20 PRU0 General-Purpose Output O AD3
pr1_pru0_gpi0 PRU0 General-Purpose Input I AH6
pr1_pru0_gpi1 PRU0 General-Purpose Input I AH3
pr1_pru0_gpi2 PRU0 General-Purpose Input I AH5
pr1_pru0_gpi3 PRU0 General-Purpose Input I AG6
pr1_pru0_gpi4 PRU0 General-Purpose Input I AH4
pr1_pru0_gpi5 PRU0 General-Purpose Input I AG4
pr1_pru0_gpi6 PRU0 General-Purpose Input I AG2
pr1_pru0_gpi7 PRU0 General-Purpose Input I AG3
pr1_pru0_gpi8 PRU0 General-Purpose Input I AG5
pr1_pru0_gpi9 PRU0 General-Purpose Input I AF2
pr1_pru0_gpi10 PRU0 General-Purpose Input I AF6
pr1_pru0_gpi11 PRU0 General-Purpose Input I AF3
pr1_pru0_gpi12 PRU0 General-Purpose Input I AF4
pr1_pru0_gpi13 PRU0 General-Purpose Input I AF1
pr1_pru0_gpi14 PRU0 General-Purpose Input I AE3
pr1_pru0_gpi15 PRU0 General-Purpose Input I AE5
pr1_pru0_gpi16 PRU0 General-Purpose Input I AE1
pr1_pru0_gpi17 PRU0 General-Purpose Input I AE2
pr1_pru0_gpi18 PRU0 General-Purpose Input I AE6
pr1_pru0_gpi19 PRU0 General-Purpose Input I AD2
pr1_pru0_gpi20 PRU0 General-Purpose Input I AD3
pr1_pru1_gpo0 PRU1 General-Purpose Output O E2
pr1_pru1_gpo1 PRU1 General-Purpose Output O D2
pr1_pru1_gpo2 PRU1 General-Purpose Output O F4
pr1_pru1_gpo3 PRU1 General-Purpose Output O C1
pr1_pru1_gpo4 PRU1 General-Purpose Output O E4
pr1_pru1_gpo5 PRU1 General-Purpose Output O F5
pr1_pru1_gpo6 PRU1 General-Purpose Output O E6
pr1_pru1_gpo7 PRU1 General-Purpose Output O D3
pr1_pru1_gpo8 PRU1 General-Purpose Output O F6
pr1_pru1_gpo9 PRU1 General-Purpose Output O D5
pr1_pru1_gpo10 PRU1 General-Purpose Output O C2
pr1_pru1_gpo11 PRU1 General-Purpose Output O C3
pr1_pru1_gpo12 PRU1 General-Purpose Output O C4
pr1_pru1_gpo13 PRU1 General-Purpose Output O B2
pr1_pru1_gpo14 PRU1 General-Purpose Output O D6
pr1_pru1_gpo15 PRU1 General-Purpose Output O C5
pr1_pru1_gpo16 PRU1 General-Purpose Output O A3
pr1_pru1_gpo17 PRU1 General-Purpose Output O B3
pr1_pru1_gpo18 PRU1 General-Purpose Output O B4
pr1_pru1_gpo19 PRU1 General-Purpose Output O B5
pr1_pru1_gpo20 PRU1 General-Purpose Output O A4
pr1_pru1_gpi0 PRU1 General-Purpose Input I E2
pr1_pru1_gpi1 PRU1 General-Purpose Input I D2
pr1_pru1_gpi2 PRU1 General-Purpose Input I F4
pr1_pru1_gpi3 PRU1 General-Purpose Input I C1
pr1_pru1_gpi4 PRU1 General-Purpose Input I E4
pr1_pru1_gpi5 PRU1 General-Purpose Input I F5
pr1_pru1_gpi6 PRU1 General-Purpose Input I E6
pr1_pru1_gpi7 PRU1 General-Purpose Input I D3
pr1_pru1_gpi8 PRU1 General-Purpose Input I F6
pr1_pru1_gpi9 PRU1 General-Purpose Input I D5
pr1_pru1_gpi10 PRU1 General-Purpose Input I C2
pr1_pru1_gpi11 PRU1 General-Purpose Input I C3
pr1_pru1_gpi12 PRU1 General-Purpose Input I C4
pr1_pru1_gpi13 PRU1 General-Purpose Input I B2
pr1_pru1_gpi14 PRU1 General-Purpose Input I D6
pr1_pru1_gpi15 PRU1 General-Purpose Input I C5
pr1_pru1_gpi16 PRU1 General-Purpose Input I A3
pr1_pru1_gpi17 PRU1 General-Purpose Input I B3
pr1_pru1_gpi18 PRU1 General-Purpose Input I B4
pr1_pru1_gpi19 PRU1 General-Purpose Input I B5
pr1_pru1_gpi20 PRU1 General-Purpose Input I A4
pr1_mii_mt0_clk MII0 Transmit Clock I U5
pr1_mii0_txen MII0 Transmit Enable O V3
pr1_mii0_txd3 MII0 Transmit Data O V5
pr1_mii0_txd2 MII0 Transmit Data O V4
pr1_mii0_txd1 MII0 Transmit Data O Y2
pr1_mii0_txd0 MII0 Transmit Data O W2
pr1_mii0_rxdv MII0 Data Valid I V2
pr1_mii_mr0_clk MII0 Receive Clock I Y1
pr1_mii0_rxd3 MII0 Receive Data I W9
pr1_mii0_rxd2 MII0 Receive Data I V9
pr1_mii0_crs MII0 Carrier Sense I V7
pr1_mii0_rxer MII0 Receive Error I U7
pr1_mii0_rxd1 MII0 Receive Data I V6
pr1_mii0_rxd0 MII0 Receive Data I U6
pr1_mii0_col MII0 Collision Detect I V1
pr1_mii0_rxlink MII0 Receive Link I U4
pr1_mii_mt1_clk MII1 Transmit Clock I C1
pr1_mii1_txen MII1 Transmit Enable O E4
pr1_mii1_txd3 MII1 Transmit Data O F5
pr1_mii1_txd2 MII1 Transmit Data O E6
pr1_mii1_txd1 MII1 Transmit Data O D5
pr1_mii1_txd0 MII1 Transmit Data O C2
pr1_mii_mr1_clk MII1 Receive Clock I C3
pr1_mii1_rxdv MII1 Data Valid I C4
pr1_mii1_rxd3 MII1 Receive Data I B2
pr1_mii1_rxd2 MII1 Receive Data I D6
pr1_mii1_rxd1 MII1 Receive Data I C5
pr1_mii1_rxd0 MII1 Receive Data I A3
pr1_mii1_rxer MII1 Receive Error I B3
pr1_mii1_rxlink MII1 Receive Link I B4
pr1_mii1_col MII1 Collision Detect I B5
pr1_mii1_crs MII1 Carrier Sense I A4
pr1_mdio_mdclk MDIO Clock O D3
pr1_mdio_data MDIO Data IO F6
pr1_edc_latch0_in Latch Input 0 I AG3 / E2
pr1_edc_latch1_in Latch Input 1 I AG5
pr1_edc_sync0_out SYNC 0 Output O AF2 / D2
pr1_edc_sync1_out SYNC 1 Output O AF6
pr1_edio_latch_in Latch Input I AF3
pr1_edio_sof Start Of Frame O AF4 / F4
pr1_edio_data_in0 Ethernet Digital Input I AF1 / E1
pr1_edio_data_in1 Ethernet Digital Input I AE3 / G2
pr1_edio_data_in2 Ethernet Digital Input I AE5 / H7
pr1_edio_data_in3 Ethernet Digital Input I AE1 / G1
pr1_edio_data_in4 Ethernet Digital Input I AE2 / G6
pr1_edio_data_in5 Ethernet Digital Input I AE6 / F2
pr1_edio_data_in6 Ethernet Digital Input I AD2 / F3
pr1_edio_data_in7 Ethernet Digital Input I AD3 / D1
pr1_edio_data_out0 Ethernet Digital Output O AF1 / E1
pr1_edio_data_out1 Ethernet Digital Output O AE3 / G2
pr1_edio_data_out2 Ethernet Digital Output O AE5 / H7
pr1_edio_data_out3 Ethernet Digital Output O AE1 / G1
pr1_edio_data_out4 Ethernet Digital Output O AE2 / G6
pr1_edio_data_out5 Ethernet Digital Output O AE6 / F2
pr1_edio_data_out6 Ethernet Digital Output O AD2 / F3
pr1_edio_data_out7 Ethernet Digital Output O AD3 / D1
pr1_uart0_cts_n UART Clear to Send I G1 / F11
pr1_uart0_rts_n UART Ready to Send O G6 / G10
pr1_uart0_rxd UART Receive Data I F2 / F10
pr1_uart0_txd UART Transmit Data O F3 / G11
pr1_ecap0_ecap_capin_apwm_o Capture Input / PWM output IO D1 / E9
PRU-ICSS 2
pr2_pru0_gpo0 PRU0 General-Purpose Output O G11 / AC5
pr2_pru0_gpo1 PRU0 General-Purpose Output O E9 / AB4
pr2_pru0_gpo2 PRU0 General-Purpose Output O F9 / AD4
pr2_pru0_gpo3 PRU0 General-Purpose Output O F8 / AC4
pr2_pru0_gpo4 PRU0 General-Purpose Output O E7 / AC7
pr2_pru0_gpo5 PRU0 General-Purpose Output O E8 / AC6
pr2_pru0_gpo6 PRU0 General-Purpose Output O D9 / AC9
pr2_pru0_gpo7 PRU0 General-Purpose Output O D7 / AC3
pr2_pru0_gpo8 PRU0 General-Purpose Output O D8 / AC8
pr2_pru0_gpo9 PRU0 General-Purpose Output O A5 / AD6
pr2_pru0_gpo10 PRU0 General-Purpose Output O C6 / AB8
pr2_pru0_gpo11 PRU0 General-Purpose Output O C8 / AB5
pr2_pru0_gpo12 PRU0 General-Purpose Output O C7 / B18
pr2_pru0_gpo13 PRU0 General-Purpose Output O B7 / F15
pr2_pru0_gpo14 PRU0 General-Purpose Output O B8 / B19
pr2_pru0_gpo15 PRU0 General-Purpose Output O A7 / C17
pr2_pru0_gpo16 PRU0 General-Purpose Output O A8 / C15
pr2_pru0_gpo17 PRU0 General-Purpose Output O C9 / A16
pr2_pru0_gpo18 PRU0 General-Purpose Output O A9 / A19
pr2_pru0_gpo19 PRU0 General-Purpose Output O B9 / A18
pr2_pru0_gpo20 PRU0 General-Purpose Output O A10 / F14
pr2_pru0_gpi0 PRU0 General-Purpose Input I G11 / AC5
pr2_pru0_gpi1 PRU0 General-Purpose Input I E9 / AB4
pr2_pru0_gpi2 PRU0 General-Purpose Input I F9 / AD4
pr2_pru0_gpi3 PRU0 General-Purpose Input I F8 / AC4
pr2_pru0_gpi4 PRU0 General-Purpose Input I E7 / AC7
pr2_pru0_gpi5 PRU0 General-Purpose Input I E8 / AC6
pr2_pru0_gpi6 PRU0 General-Purpose Input I D9 / AC9
pr2_pru0_gpi7 PRU0 General-Purpose Input I D7 / AC3
pr2_pru0_gpi8 PRU0 General-Purpose Input I D8 / AC8
pr2_pru0_gpi9 PRU0 General-Purpose Input I A5 / AD6
pr2_pru0_gpi10 PRU0 General-Purpose Input I C6 / AB8
pr2_pru0_gpi11 PRU0 General-Purpose Input I C8 / AB5
pr2_pru0_gpi12 PRU0 General-Purpose Input I C7 / B18
pr2_pru0_gpi13 PRU0 General-Purpose Input I B7 / F15
pr2_pru0_gpi14 PRU0 General-Purpose Input I B8 / B19
pr2_pru0_gpi15 PRU0 General-Purpose Input I A7 / C17
pr2_pru0_gpi16 PRU0 General-Purpose Input I A8 / C15
pr2_pru0_gpi17 PRU0 General-Purpose Input I C9 / A16
pr2_pru0_gpi18 PRU0 General-Purpose Input I A9 / A19
pr2_pru0_gpi19 PRU0 General-Purpose Input I B9 / A18
pr2_pru0_gpi20 PRU0 General-Purpose Input I A10 / F14
pr2_pru1_gpo0 PRU1 General-Purpose Output O V1 / D17
pr2_pru1_gpo1 PRU1 General-Purpose Output O U4 / AA3
pr2_pru1_gpo2 PRU1 General-Purpose Output O U3 / AB9
pr2_pru1_gpo3 PRU1 General-Purpose Output O V2 / AB3
pr2_pru1_gpo4 PRU1 General-Purpose Output O Y1 / AA4
pr2_pru1_gpo5 PRU1 General-Purpose Output O W9 / D18
pr2_pru1_gpo6 PRU1 General-Purpose Output O V9 / E17
pr2_pru1_gpo7 PRU1 General-Purpose Output O V7 / C14
pr2_pru1_gpo8 PRU1 General-Purpose Output O U7 / G12
pr2_pru1_gpo9 PRU1 General-Purpose Output O V6 / F12
pr2_pru1_gpo10 PRU1 General-Purpose Output O U6 / B12
pr2_pru1_gpo11 PRU1 General-Purpose Output O U5 / A11
pr2_pru1_gpo12 PRU1 General-Purpose Output O V5 / B13
pr2_pru1_gpo13 PRU1 General-Purpose Output O V4 / A12
pr2_pru1_gpo14 PRU1 General-Purpose Output O V3 / E14
pr2_pru1_gpo15 PRU1 General-Purpose Output O Y2 / A13
pr2_pru1_gpo16 PRU1 General-Purpose Output O W2 / G14
pr2_pru1_gpo17 PRU1 General-Purpose Output O E11
pr2_pru1_gpo18 PRU1 General-Purpose Output O F11
pr2_pru1_gpo19 PRU1 General-Purpose Output O G10
pr2_pru1_gpo20 PRU1 General-Purpose Output O F10
pr2_pru1_gpi0 PRU1 General-Purpose Input I V1 / D17
pr2_pru1_gpi1 PRU1 General-Purpose Input I U4 / AA3
pr2_pru1_gpi2 PRU1 General-Purpose Input I U3 / AB9
pr2_pru1_gpi3 PRU1 General-Purpose Input I V2 / AB3
pr2_pru1_gpi4 PRU1 General-Purpose Input I Y1 / AA4
pr2_pru1_gpi5 PRU1 General-Purpose Input I W9 / D18
pr2_pru1_gpi6 PRU1 General-Purpose Input I V9 / E17
pr2_pru1_gpi7 PRU1 General-Purpose Input I V7 / C14
pr2_pru1_gpi8 PRU1 General-Purpose Input I U7 / G12
pr2_pru1_gpi9 PRU1 General-Purpose Input I V6 / F12
pr2_pru1_gpi10 PRU1 General-Purpose Input I U6 / B12
pr2_pru1_gpi11 PRU1 General-Purpose Input I U5 / A11
pr2_pru1_gpi12 PRU1 General-Purpose Input I V5 / B13
pr2_pru1_gpi13 PRU1 General-Purpose Input I V4 / A12
pr2_pru1_gpi14 PRU1 General-Purpose Input I V3 / E14
pr2_pru1_gpi15 PRU1 General-Purpose Input I Y2 / A13
pr2_pru1_gpi16 PRU1 General-Purpose Input I W2 / G14
pr2_pru1_gpi17 PRU1 General-Purpose Input I E11
pr2_pru1_gpi18 PRU1 General-Purpose Input I F11
pr2_pru1_gpi19 PRU1 General-Purpose Input I G10
pr2_pru1_gpi20 PRU1 General-Purpose Input I F10
pr2_edc_latch0_in Latch Input 0 I F9
pr2_edc_latch1_in Latch Input 1 I F8
pr2_edc_sync0_out SYNC 0 Output O E7
pr2_edc_sync1_out SYNC 1 Output O E8
pr2_edio_latch_in Latch Input I D9
pr2_edio_sof Start Of Frame O D7
pr2_uart0_cts_n UART Clear-To-Send I D8
pr2_uart0_rts_n UART Ready-To-Send O A5
pr2_uart0_rxd UART Receive Data I C6
pr2_uart0_txd UART Transmit Data O C8
pr2_ecap0_ecap_capin_apwm_o Capture Input / PWM output IO C7
pr2_edio_data_in0 Ethernet Digital Input I B7
pr2_edio_data_in1 Ethernet Digital Input I B8
pr2_edio_data_in2 Ethernet Digital Input I A7
pr2_edio_data_in3 Ethernet Digital Input I A8
pr2_edio_data_in4 Ethernet Digital Input I C9
pr2_edio_data_in5 Ethernet Digital Input I A9
pr2_edio_data_in6 Ethernet Digital Input I B9
pr2_edio_data_in7 Ethernet Digital Input I A10
pr2_edio_data_out0 Ethernet Digital Output O B7
pr2_edio_data_out1 Ethernet Digital Output O B8
pr2_edio_data_out2 Ethernet Digital Output O A7
pr2_edio_data_out3 Ethernet Digital Output O A8
pr2_edio_data_out4 Ethernet Digital Output O C9
pr2_edio_data_out5 Ethernet Digital Output O A9
pr2_edio_data_out6 Ethernet Digital Output O B9
pr2_edio_data_out7 Ethernet Digital Output O A10
pr2_mii1_col MII1 Collision Detect I D18
pr2_mii1_crs MII1 Carrier Sense I E17
pr2_mdio_mdclk MDIO Clock O C14 / AB3
pr2_mdio_data MDIO Data IO D14 / AA4
pr2_mii0_rxer MII0 Receive Error I G12
pr2_mii_mt0_clk MII0 Transmit Clock I F12
pr2_mii0_txen MII0 Transmit Enable O B12
pr2_mii0_txd3 MII0 Transmit Data O A11
pr2_mii0_txd2 MII0 Transmit Data O B13
pr2_mii0_txd1 MII0 Transmit Data O A12
pr2_mii0_txd0 MII0 Transmit Data O E14
pr2_mii_mr0_clk MII0 Receive Clock I A13
pr2_mii0_rxdv MII0 Data Valid I G14
pr2_mii0_rxd3 MII0 Receive Data I F14
pr2_mii0_rxd2 MII0 Receive Data I A19
pr2_mii0_rxd1 MII0 Receive Data I A18
pr2_mii0_rxd0 MII0 Receive Data I C15
pr2_mii0_rxlink MII0 Receive Link I A16
pr2_mii0_crs MII0 Carrier Sense I B18
pr2_mii0_col MII0 Collision Detect I F15
pr2_mii1_rxer MII1 Receive Error I B19
pr2_mii1_rxlink MII1 Receive Link I C17
pr2_mii_mt1_clk MII1 Transmit Clock I AC5
pr2_mii1_txen MII1 Transmit Enable O AB4
pr2_mii1_txd3 MII1 Transmit Data O AD4
pr2_mii1_txd2 MII1 Transmit Data O AC4
pr2_mii1_txd1 MII1 Transmit Data O AC7
pr2_mii1_txd0 MII1 Transmit Data O AC6
pr2_mii_mr1_clk MII1 Receive Clock I AC9
pr2_mii1_rxdv MII1 Data Valid I AC3
pr2_mii1_rxd3 MII1 Receive Data I AC8
pr2_mii1_rxd2 MII1 Receive Data I AD6
pr2_mii1_rxd1 MII1 Receive Data I AB8
pr2_mii1_rxd0 MII1 Receive Data I AB5

NOTE

PRU-ICSS has internal multiplexing capability of pin functions. See PRU-ICSS Internal Pinmux in the device TRM. Besides, EGPIO module can be configured to export additional functions to EGPIO pins in place of simple GPIO. See Enhanced General-Purpose Module/Serial Capture Unit in the device TRM.