5.10.3 Power Supply Sequences

This section describes the power-up and power-down sequence required to ensure proper device operation. The power supply names described in this section comprise a superset of a family of compatible devices. Some members of this family will not include a subset of these power supplies and their associated device modules. Refer to the Section 4.2, Pin Attributes of the Section 4, Terminal Configuration and Functions to determine which power supplies are applicable.

Figure 5-5 and Figure 5-6 describe the device power sequencing when RTC-mode is NOT used.

Figure 5-5 Power-Up Sequencing⁽²⁾

1. Grey shaded areas are windows where it is valid to ramp the voltage rail.
2. Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
3. If RTC-only mode is not used then the following combinations are approved:
   - vdda_rtc can be combined with vdds18v
   - vdd_rtc can be combined with vdd
   - vddshv5 can be combined with other 1.8 V or 3.3 V vddshvn rails.
   If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements. When using RTC mode timing:
   - vdda_rtc rises coincident with, or before, the 1.8 V interface supplies (such as vdds18v).
   - vdd_rtc rises coincident with vdd, or it may rise earlier. If rising earlier, it must rise after the 1.8 V interface supplies.
   - vddshv5 rises coincident with the other vddshvn rails (of the same voltage) or it can rise about the same time as the 1.8 V PHY supplies (such as vdd_usb1).
   
4. vdd must ramp before or at the same time as vdd_mpu, vdd_gpu, vdd_dspeve and vdd_iva.
5. vdd_mpu, vdd_gpu, vdd_dspeve, vdd_iva can be ramped at the same time or can be staggered.
6. If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8 V only, then these rails can be combined with vdds18v.
7. vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn rails but vddshv8 must ramp after vdd.
8. vdds and vdda rails must not be combined together, with the one exception of vdda_rtc when RTC-mode is not supported.
9. Pulse duration: rtc_porz must remain low 1 ms after vdda_rtc, vddshv5, and vdd_rtc are ramped and stable.
10. The FUNC_32K_CLK source must be stable and at a valid frequency 1ms prior to deasserting rtc_porz high.
11. porz must remain asserted low until all of the following conditions are met:
    • All device supply rails reach stable operational levels.
    • xi_osc0 is stable and at a valid frequency.
    • Minimum of 12P after both of the above conditions are met, where P = 1 / (SYS_CLK1/610), units in ns.
    resetn must be high prior to, or rise simultaneous with, porz but not before its power supply, vddshv3, rising.
12. Setup time: sysboot[15:0] pins must be valid 2P⁽¹⁵⁾ before porz is de-asserted high.
13. Hold time: sysboot[15:0] pins must be valid 15P⁽¹⁵⁾ after porz is de-asserted high.
14. rstoutn will be asserted low when porz is low, and de-asserted following an internal 2ms delay. rstoutn is only valid after vddshv3 reaches an operational level. If used as a peripheral component reset, it should be AND gated with porz to avoid possible reset glitches during power up.
15. P = 1 / (SYS_CLK1 / 610) µs, where SYS_CLK1 is in MHz.
16. ddr1_vref0 / ddr2_vref0 may rise coincident with vdds_ddr1 / vdds_ddr2, respectively or at a later time. However, it must be valid before porz rising.

Figure 5-6 Power-Down Sequencing^(12)(14)

1. Grey shaded areas are windows where it is valid to ramp the voltage rail.
2. Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
3. xi_osc0 can be turned off anytime after porz assertion and must be turned off before vdda_osc voltage rail is shutdown.
4. If RTC-mode is not used then the following combinations are approved:
   - vdda_rtc can be combined with vdds18v
   - vdd_rtc can be combined with vdd
   - vddshv5 can be combined with other 1.8 V or 3.3 V vddshv* rails
   If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements. When using RTC mode timing:
   - vdda_rtc falls coincident with, or later than, the 1.8 V interface supplies (such as vdds18v).
   - vdd_rtc falls coincident with vdd, or it may fall later. If falling later, it must fall before, or coincident with, the 1.8 V interface supplies.
   - vddshv5 falls coincident with the other vddshvn rails (of the same voltage) or it can fall about the same time as the 1.8 V PHY supplies (such as vdd_usb1).
   
5. vddshv* domains supplied by 3.3 V:
   • must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100 µs min after porz is asserted low.
   • must be in first group of supplies ramping down after porz has been asserted low for 100 µs min.
   • must not exceed vdds18v by more than 2 V during ramp down, see Figure 5-7 “vdds18v versus vddshv* Discharge Relationship”.
6. vdd_mpu, vdd_gpu, vdd_dspeve, vdd_iva can be ramped at the same time or can be staggered.
7. vddshv8 domain:
   • if SDIO operation is needed,
     • must be in first group of supplies to ramp down after porz has been asserted low for 100 µs min.
     • must be sourced from independent power resource that can provide dual voltage (3.3 V / 1.8 V) operation as required to be compliant to SDIO specification
   • if SDIO operation is not needed,
     • must be grouped and ramped down with other vddshv* domains as noted above.
8. vdd must ramp after or at the same time as vdd_mpu, vdd_gpu, vdd_dspeve and vdd_iva.
9. If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8 V only, then these rails can be combined with vdds18v. vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8 V mode or in 3.3 V mode. If vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must ensure that the vddshv[1-7,9-11] rail is never higher than 2.0 V above the vdds18v rail.
10. vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other vddshv[1-7,9-11] rails, then it is allowed to ramp down at either of the last two points in the timing diagram.
11. The 1.8 V vdda_* supplies can either ramp down at the earlier time period shown or can be delayed to ramp down after the core supplies coincident with the vdds18v supply as long as porz is asserted (low) during the power down sequence.
12. The power down sequence shown is the most general case and is always valid. An accelerated power down sequence is also available but is only valid when porz is asserted (low). This accelerated power down sequence has been implemented in the companion PMIC that is recommended for use with this SoC. The accelerated sequence has porz go low first, then all 3.3 V supplies simultaneously second, core supplies, DDR supplies and DDR references simultaneously third and all 1.8 V supplies simultaneously last.
13. ddr1_vref0 / ddr2_vref0 may fall coincident with vdds_ddr1 / vdds_ddr2, respectively or at a prior time but after porz is asserted low.
14. Ramped Down is defined as reaching a voltage level of no more than 0.6 V.

Figure 5-7 describes the discharge relationship between vdds18v and vddshv* power supplies during power-down.

Figure 5-7 vdds18v versus vddshv* Discharge Relationship

1. Vdelta MAX = 2 V
2. If vddshv8 is powered by the same supply source as the other vddshv[1-7,9-11] rails.