SPRSP98A November   2023  – June 2024 AM625SIP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes and Signal Descriptions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Operating Performance Points
    5. 6.5 Thermal Resistance Characteristics
      1. 6.5.1 Thermal Resistance Characteristics for AMK Package
    6. 6.6 Timing and Switching Characteristics
      1. 6.6.1 Power Supply Requirements
        1. 6.6.1.1 Power Supply Sequencing
  8. 7 Applications, Implementation, and Layout
    1. 7.1 Peripheral- and Interface-Specific Design Information
      1. 7.1.1 Integrated LPDDR4 SDRAM Information
  9. 8 Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • AMK|425
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Device Comparison

Table 4-1 shows a comparison between devices, highlighting the differences.

Note: Availability of features listed in this table are a function of shared IO pins, where IO signals associated with many of the features are multiplexed to a limited number of pins. The SysConfig tool should be used to assign signal functions to pins. This will provide a better understanding of limitations associated with pin multiplexing.
Note: To understand what device features are currently supported by TI Software Development Kits (SDKs), search for the AM62x Software Build Sheet located in the Downloads tab option provided at Processor-SDK-AM62x.
Table 4-1 Device Comparison
FEATURES REFERENCE
NAME		 AM625SIP AM625(1)
AM6254 AM6254
WKUP_CTRL_MMR_CFG0_JTAG_USER_ID[31:13](2)
Register bit values by device "Features" code (See Device Naming Convention for more information on device features)
C: - 0x1D123
G: - 0x1D127
L: 0x1F120 -
PROCESSORS AND ACCELERATORS
Speed Grades (See Device Speed Grades) T T, S, K, G
Arm Cortex-A53
Microprocessor Subsystem		 Arm A53 Quad Core
Arm Cortex-M4F
in MCU domain		 Arm M4F Single Core
No Functional Safety		 Single Core
Functional Safety (Optional)
3D Graphics Engine
(OpenGL ES 3.1, Vulkan 1.2)		 3D Graphics engine Yes
Device Management Subsystem WKUP_R5F Single core
Crypto Accelerators Security Yes
PROGRAM AND DATA STORAGE
On-Chip Shared Memory (RAM) in MAIN Domain OCSRAM 64KB (with SECDED ECC)
On-Chip Shared Memory (RAM) in M4F Domain MCU_MSRAM 256KB
DDR4/LPDDR4 DDR Subsystem DDRSS Integrated 512MB LPDDR4 SDRAM 16-bit data with inline ECC;
up to 8GB using DDR4 or
up to 4GB using LPDDR4
General-Purpose Memory Controller GPMC Up to 1GB with ECC
PERIPHERALS
Display Subsystem DSS 1x DPI
1x LVDS
Modular Controller Area Network Interface with Full CAN-FD Support MCAN 3
General-Purpose I/O GPIO Up to 170
Inter-Integrated Circuit Interface I2C 6
Multichannel Audio Serial Port MCASP 3
Multichannel Serial Peripheral Interface MCSPI 5
Multi-Media Card/ Secure Digital Interface MM/CSD 1x eMMC (8-bits)
2x SD/SDIO (4-bits)
Flash Subsystem (FSS)(3) OSPI0/QSPI0 Yes(3)
Programmable Real-Time Unit Subsystem PRUSS 2x PRU Cores 2x PRU Cores (Optional)
Industrial Communication Subsystem Support(4) PRUSS No
Gigabit Ethernet Interface CPSW3G Yes
General-Purpose Timers TIMER 12 (4 in MCU Channel)
Enhanced Pulse-Width Modulator Module EPWM 3
Enhanced Capture Module ECAP 3
Enhanced Quadrature Encoder Pulse Module EQEP 3
Universal Asynchronous Receiver and Transmitter UART 9
CSI2-RX Controller with DPHY CSI-RX 1
USB2.0 Controller with PHY USB 2.0 2
(1) This column is only provided as a quick reference of device feature relative to the AM625 family of devices. Refer to the AM62x Sitara Processors Datasheet for more information on AM625 feature codes, speed grades, and optional features.
(2) For more details about the WKUP_MMR0_JTAG_USER_ID register and DEVICE_ID bit field, see the device TRM.
(3) One flash interface, configured as OSPI0 or QSPI0.
(4) Industrial Communication Subsystem support is not available for this family of devices.