ZHCSTX4 数据表 | 德州仪器 TI.com.cn

SPRSP98A November 2023 – June 2024 AM625SIP

PRODUCTION DATA

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

AMK|425

Thermal pad, mechanical data (Package|Pins)

Orderable Information

sprsp98a_oa

6.4 Operating Performance Points

This section describes maximum operating conditions of the device in Table 6-1 and describes each Operating Performance Point (OPP) for processor clocks and device core clocks in Table 6-2.

Table 6-1 Device Speed Grades

Speed Grade	VDD_CORE (V)⁽¹⁾	MAXIMUM OPERATING FREQUENCY (MHz)								MAXIMUM TRANSITION RATE (MT/s)
Speed Grade	VDD_CORE (V)⁽¹⁾	A53SS (Cortex-A53x)	GPU	PRU	Main Infra (CBA)	MCUSS (Cortex-M4F)	Device/ Power Manager (Cortex-R5F)	SMS Subsystem (Dual Cortex-M4F)	OCSRAM	LPDDR4
T	0.75/0.85	1250	500	333	250	400	400	400	400	1600
T	0.85	1400	500	333	250	400	400	400	400	1600

(1) Nominal operating voltage, see Recommended Operating Conditions.

Table 6-2 Device Operating Performance Points

OPP	A53SS⁽¹⁾	FIXED OPERATING FREQUENCY OPTIONS (MHz)⁽²⁾							MT/s
OPP	A53SS⁽¹⁾	GPU	PRU	MAIN INFRA (CBA)	MCUSS	DEVICE/ POWER MANAGER	SMS / SMS CBA	OCSRAM	LPDDR4
High	From ARM0 PLL Bypass to Speed Grade Maximum	500	333, 250, or 200	250	400 or 200	400	400	400	From DDR PLL Bypass⁽³⁾ to 1600
Low	From ARM0 PLL Bypass to Speed Grade Maximum	N/A	333, 250, or 200	125	400 or 200	133	133	133	From DDR PLL Bypass⁽³⁾ to 1600

(1) Default operating frequency, set by software at boot. Supports Dynamic Frequency Scaling after boot.

(2) Fixed operating frequency, set by software at boot.

(3) The DDR PLL output, which sources DDR0_CK0 and DDR0_CK0_n, is typically defined in units of frequency. So the "DDR PLL Bypass" transaction rate is equal to 2x the DDR PLL output frequency when operating in bypass mode.