SPRSP56G January 2021 – April 2024 AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
SIGNAL NAME [1] | PIN TYPE [2] | DESCRIPTION [3] | ALV PIN [4] |
---|---|---|---|
CLKOUT0 | O | RMII Clock Output (50 MHz). This pin is used for clock source to the external PHY and must be routed back to the RMII_REF_CLK pin for proper device operation. | A19, U13 |
EXTINTn | I | External Interrupt | C19 |
EXT_REFCLK1 | I | External clock input to Main Domain, routed to Timer clock muxes as one of the selectable input clock sources for Timer/WDT modules, or as reference clock to MAIN_PLL2 (PER1 PLL) | A19 |
OBSCLK0 | O | Observation clock output for test and debug purposes only | D17 |
PORz_OUT | O | Main Domain POR status output | E17 |
RESETSTATz | O | Main Domain warm reset status output | F16 |
RESET_REQz | I | Main Domain external warm reset request input | E18 |
SYSCLKOUT0 | O | SYSCLK0 output from Main PLL controller (divided by 6) for test and debug purposes only | C17 |