SPRSP56G January   2021  – April 2024 AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
      1.      11
      2.      12
    3. 5.3 Signal Descriptions
      1.      14
      2. 5.3.1  ADC
        1. 5.3.1.1 MAIN Domain
          1.        17
      3. 5.3.2  CPSW3G
        1. 5.3.2.1 MAIN Domain
          1.        20
          2.        21
          3.        22
      4. 5.3.3  CPTS
        1. 5.3.3.1 MAIN Domain
          1.        25
          2.        26
      5. 5.3.4  DDRSS
        1. 5.3.4.1 MAIN Domain
          1.        29
      6. 5.3.5  ECAP
        1. 5.3.5.1 MAIN Domain
          1.        32
          2.        33
          3.        34
      7. 5.3.6  Emulation and Debug
        1. 5.3.6.1 MAIN Domain
          1.        37
        2. 5.3.6.2 MCU Domain
          1.        39
      8. 5.3.7  EPWM
        1. 5.3.7.1 MAIN Domain
          1.        42
          2.        43
          3.        44
          4.        45
          5.        46
          6.        47
          7.        48
          8.        49
          9.        50
          10.        51
      9. 5.3.8  EQEP
        1. 5.3.8.1 MAIN Domain
          1.        54
          2.        55
          3.        56
      10. 5.3.9  FSI
        1. 5.3.9.1 MAIN Domain
          1.        59
          2.        60
          3.        61
          4.        62
          5.        63
          6.        64
          7.        65
          8.        66
      11. 5.3.10 GPIO
        1. 5.3.10.1 MAIN Domain
          1.        69
          2.        70
        2. 5.3.10.2 MCU Domain
          1.        72
      12. 5.3.11 GPMC
        1. 5.3.11.1 MAIN Domain
          1.        75
      13. 5.3.12 I2C
        1. 5.3.12.1 MAIN Domain
          1.        78
          2.        79
          3.        80
          4.        81
        2. 5.3.12.2 MCU Domain
          1.        83
          2.        84
      14. 5.3.13 MCAN
        1. 5.3.13.1 MAIN Domain
          1.        87
          2.        88
      15. 5.3.14 MCSPI
        1. 5.3.14.1 MAIN Domain
          1.        91
          2.        92
          3.        93
          4.        94
          5.        95
        2. 5.3.14.2 MCU Domain
          1.        97
          2.        98
      16. 5.3.15 MDIO
        1. 5.3.15.1 MAIN Domain
          1.        101
      17. 5.3.16 MMC
        1. 5.3.16.1 MAIN Domain
          1.        104
          2.        105
      18. 5.3.17 OSPI
        1. 5.3.17.1 MAIN Domain
          1.        108
      19. 5.3.18 Power Supply
        1.       110
      20. 5.3.19 PRU_ICSSG
        1. 5.3.19.1 MAIN Domain
          1.        113
          2.        114
      21. 5.3.20 Reserved
        1.       116
      22. 5.3.21 SERDES
        1. 5.3.21.1 MAIN Domain
          1.        119
      23. 5.3.22 System and Miscellaneous
        1. 5.3.22.1 Boot Mode Configuration
          1. 5.3.22.1.1 MAIN Domain
            1.         123
        2. 5.3.22.2 Clock
          1. 5.3.22.2.1 MCU Domain
            1.         126
        3. 5.3.22.3 System
          1. 5.3.22.3.1 MAIN Domain
            1.         129
          2. 5.3.22.3.2 MCU Domain
            1.         131
        4. 5.3.22.4 VMON
          1.        133
      24. 5.3.23 TIMER
        1. 5.3.23.1 MAIN Domain
          1.        136
        2. 5.3.23.2 MCU Domain
          1.        138
      25. 5.3.24 UART
        1. 5.3.24.1 MAIN Domain
          1.        141
          2.        142
          3.        143
          4.        144
          5.        145
          6.        146
          7.        147
        2. 5.3.24.2 MCU Domain
          1.        149
          2.        150
      26. 5.3.25 USB
        1. 5.3.25.1 MAIN Domain
          1.        153
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On Hours (POH)
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Operating Performance Points
    6. 6.6  Power Consumption Summary
    7. 6.7  Electrical Characteristics
      1. 6.7.1  I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.7.2  Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 6.7.3  High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 6.7.4  eMMCPHY Electrical Characteristics
      5. 6.7.5  SDIO Electrical Characteristics
      6. 6.7.6  LVCMOS Electrical Characteristics
      7. 6.7.7  ADC12B Electrical Characteristics
      8. 6.7.8  USB2PHY Electrical Characteristics
      9. 6.7.9  SerDes PHY Electrical Characteristics
      10. 6.7.10 DDR Electrical Characteristics
    8. 6.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.8.2 Hardware Requirements
      3. 6.8.3 Programming Sequence
      4. 6.8.4 Impact to Your Hardware Warranty
    9. 6.9  Thermal Resistance Characteristics
      1. 6.9.1 Thermal Resistance Characteristics
    10. 6.10 Timing and Switching Characteristics
      1. 6.10.1 Timing Parameters and Information
      2. 6.10.2 Power Supply Requirements
        1. 6.10.2.1 Power Supply Slew Rate Requirement
        2. 6.10.2.2 Power Supply Sequencing
          1. 6.10.2.2.1 Power-Up Sequencing
          2. 6.10.2.2.2 Power-Down Sequencing
      3. 6.10.3 System Timing
        1. 6.10.3.1 Reset Timing
        2. 6.10.3.2 Safety Signal Timing
        3. 6.10.3.3 Clock Timing
      4. 6.10.4 Clock Specifications
        1. 6.10.4.1 Input Clocks / Oscillators
          1. 6.10.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 6.10.4.1.1.1 Load Capacitance
            2. 6.10.4.1.1.2 Shunt Capacitance
          2. 6.10.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
        2. 6.10.4.2 Output Clocks
        3. 6.10.4.3 PLLs
        4. 6.10.4.4 Recommended System Precautions for Clock and Control Signal Transitions
      5. 6.10.5 Peripherals
        1. 6.10.5.1  CPSW3G
          1. 6.10.5.1.1 CPSW3G MDIO Timing
          2. 6.10.5.1.2 CPSW3G RMII Timing
          3. 6.10.5.1.3 CPSW3G RGMII Timing
          4. 6.10.5.1.4 CPSW3G IOSETs
        2. 6.10.5.2  DDRSS
        3. 6.10.5.3  ECAP
        4. 6.10.5.4  EPWM
        5. 6.10.5.5  EQEP
        6. 6.10.5.6  FSI
        7. 6.10.5.7  GPIO
        8. 6.10.5.8  GPMC
          1. 6.10.5.8.1 GPMC and NOR Flash — Synchronous Mode
          2. 6.10.5.8.2 GPMC and NOR Flash — Asynchronous Mode
          3. 6.10.5.8.3 GPMC and NAND Flash — Asynchronous Mode
          4. 6.10.5.8.4 GPMC0 IOSETs
        9. 6.10.5.9  I2C
        10. 6.10.5.10 MCAN
        11. 6.10.5.11 MCSPI
          1. 6.10.5.11.1 MCSPI — Controller Mode
          2. 6.10.5.11.2 MCSPI — Peripheral Mode
        12. 6.10.5.12 MMCSD
          1. 6.10.5.12.1 MMC0 - eMMC Interface
            1. 6.10.5.12.1.1 Legacy SDR Mode
            2. 6.10.5.12.1.2 High Speed SDR Mode
            3. 6.10.5.12.1.3 High Speed DDR Mode
            4. 6.10.5.12.1.4 HS200 Mode
          2. 6.10.5.12.2 MMC1 - SD/SDIO Interface
            1. 6.10.5.12.2.1 Default Speed Mode
            2. 6.10.5.12.2.2 High Speed Mode
            3. 6.10.5.12.2.3 UHS–I SDR12 Mode
            4. 6.10.5.12.2.4 UHS–I SDR25 Mode
            5. 6.10.5.12.2.5 UHS–I SDR50 Mode
            6. 6.10.5.12.2.6 UHS–I DDR50 Mode
            7. 6.10.5.12.2.7 UHS–I SDR104 Mode
        13. 6.10.5.13 CPTS
        14. 6.10.5.14 OSPI
          1. 6.10.5.14.1 OSPI0 PHY Mode
            1. 6.10.5.14.1.1 OSPI0 With PHY Data Training
            2. 6.10.5.14.1.2 OSPI0 Without Data Training
              1. 6.10.5.14.1.2.1 OSPI0 PHY SDR Timing
              2. 6.10.5.14.1.2.2 OSPI0 PHY DDR Timing
          2. 6.10.5.14.2 OSPI0 Tap Mode
            1. 6.10.5.14.2.1 OSPI0 Tap SDR Timing
            2. 6.10.5.14.2.2 OSPI0 Tap DDR Timing
        15. 6.10.5.15 PCIe
        16. 6.10.5.16 PRU_ICSSG
          1. 6.10.5.16.1 PRU_ICSSG Programmable Real-Time Unit (PRU)
            1. 6.10.5.16.1.1 PRU_ICSSG PRU Direct Output Mode Timing
            2. 6.10.5.16.1.2 PRU_ICSSG PRU Parallel Capture Mode Timing
            3. 6.10.5.16.1.3 PRU_ICSSG PRU Shift Mode Timing
            4. 6.10.5.16.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface
              1. 6.10.5.16.1.4.1 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing
          2. 6.10.5.16.2 PRU_ICSSG Pulse Width Modulation (PWM)
            1. 6.10.5.16.2.1 PRU_ICSSG PWM Timing
          3. 6.10.5.16.3 PRU_ICSSG Industrial Ethernet Peripheral (IEP)
            1. 6.10.5.16.3.1 PRU_ICSSG IEP Timing
          4. 6.10.5.16.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (UART)
            1. 6.10.5.16.4.1 PRU_ICSSG UART Timing
          5. 6.10.5.16.5 PRU_ICSSG Enhanced Capture Peripheral (ECAP)
            1. 6.10.5.16.5.1 PRU_ICSSG ECAP Timing
          6. 6.10.5.16.6 PRU_ICSSG RGMII, MII_RT, and Switch
            1. 6.10.5.16.6.1 PRU_ICSSG MDIO Timing
            2. 6.10.5.16.6.2 PRU_ICSSG MII Timing
            3. 6.10.5.16.6.3 PRU_ICSSG RGMII Timing
        17. 6.10.5.17 Timers
        18. 6.10.5.18 UART
        19. 6.10.5.19 USB
      6. 6.10.6 Emulation and Debug
        1. 6.10.6.1 Trace
        2. 6.10.6.2 JTAG
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A53 Subsystem
      2. 7.2.2 Arm Cortex-R5F Subsystem (R5FSS)
      3. 7.2.3 Arm Cortex-M4F (M4FSS)
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)
    4. 7.4 Other Subsystems
      1. 7.4.1 PDMA Controller
      2. 7.4.2 Peripherals
        1. 7.4.2.1  ADC
        2. 7.4.2.2  DCC
        3. 7.4.2.3  Dual Date Rate (DDR) External Memory Interface (DDRSS)
        4. 7.4.2.4  ECAP
        5. 7.4.2.5  EPWM
        6. 7.4.2.6  ELM
        7. 7.4.2.7  ESM
        8. 7.4.2.8  GPIO
        9. 7.4.2.9  EQEP
        10. 7.4.2.10 General-Purpose Memory Controller (GPMC)
        11. 7.4.2.11 I2C
        12. 7.4.2.12 MCAN
        13. 7.4.2.13 MCRC Controller
        14. 7.4.2.14 MCSPI
        15. 7.4.2.15 MMCSD
        16. 7.4.2.16 OSPI
        17. 7.4.2.17 Peripheral Component Interconnect Express (PCIe)
        18. 7.4.2.18 Serializer/Deserializer (SerDes) PHY
        19. 7.4.2.19 Real Time Interrupt (RTI/WWDT)
        20. 7.4.2.20 Dual Mode Timer (DMTIMER)
        21. 7.4.2.21 UART
        22. 7.4.2.22 Universal Serial Bus Subsystem (USBSS)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply
        1. 8.1.1.1 Power Supply Designs
        2. 8.1.1.2 Power Distribution Network Implementation Guidance
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG, EMU, and TRACE
      4. 8.1.4 Unused Pins
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 DDR Board Design and Layout Guidelines
      2. 8.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 8.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 8.2.2.2 External Board Loopback
        3. 8.2.2.3 DQS (only available in Octal SPI devices)
      3. 8.2.3 USB VBUS Design Guidelines
      4. 8.2.4 System Power Supply Monitor Design Guidelines
      5. 8.2.5 High Speed Differential Signal Routing Guidance
      6. 8.2.6 Thermal Solution Guidance
    3. 8.3 Clock Routing Guidelines
      1. 8.3.1 Oscillator Routing
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALV|441
Thermal pad, mechanical data (Package|Pins)
Orderable Information
Table 5-60 PRU_ICSSG1 Signal Descriptions
SIGNAL NAME [1]PIN TYPE [2]DESCRIPTION [3]ALV PIN [4]
PRG1_ECAP0_IN_APWM_OUTIOPRU-ICSSG Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) OutputV12
PRG1_ECAP0_SYNC_INIPRU-ICSSG ECAP Sync Input Y13
PRG1_ECAP0_SYNC_OUTOPRU-ICSSG ECAP Sync OutputAA14
PRG1_IEP0_EDIO_OUTVALIDOPRU_ICSSG Industrial Ethernet Digital I/O OutvalidD14
PRG1_IEP0_EDC_LATCH_IN0IPRU_ICSSG Industrial Ethernet Distributed Clock Latch InputV7
PRG1_IEP0_EDC_LATCH_IN1IPRU_ICSSG Industrial Ethernet Distributed Clock Latch InputU13
PRG1_IEP0_EDC_SYNC_OUT0OPRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputW7
PRG1_IEP0_EDC_SYNC_OUT1OPRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputU7
PRG1_IEP0_EDIO_DATA_IN_OUT28IOPRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputU15
PRG1_IEP0_EDIO_DATA_IN_OUT29IOPRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputU14
PRG1_IEP0_EDIO_DATA_IN_OUT30IOPRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputV14
PRG1_IEP0_EDIO_DATA_IN_OUT31IOPRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputW14
PRG1_IEP1_EDC_LATCH_IN0IPRU_ICSSG Industrial Ethernet Distributed Clock Latch InputY13
PRG1_IEP1_EDC_LATCH_IN1IPRU_ICSSG Industrial Ethernet Distributed Clock Latch InputV15
PRG1_IEP1_EDC_SYNC_OUT0OPRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputV12
PRG1_IEP1_EDC_SYNC_OUT1OPRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputAA14
PRG1_MDIO0_MDCOPRU-ICSSG MDIO ClockY6
PRG1_MDIO0_MDIOIOPRU-ICSSG MDIO DataAA6
PRG1_PRU0_GPI0IPRU-ICSSG PRU Data InputY7
PRG1_PRU0_GPI1IPRU-ICSSG PRU Data InputU8
PRG1_PRU0_GPI2IPRU-ICSSG PRU Data InputW8
PRG1_PRU0_GPI3IPRU-ICSSG PRU Data InputV8
PRG1_PRU0_GPI4IPRU-ICSSG PRU Data InputY8
PRG1_PRU0_GPI5IPRU-ICSSG PRU Data InputV13
PRG1_PRU0_GPI6IPRU-ICSSG PRU Data InputAA7
PRG1_PRU0_GPI7IPRU-ICSSG PRU Data InputU13
PRG1_PRU0_GPI8IPRU-ICSSG PRU Data InputW13
PRG1_PRU0_GPI9IPRU-ICSSG PRU Data InputU15
PRG1_PRU0_GPI10IPRU-ICSSG PRU Data InputU14
PRG1_PRU0_GPI11IPRU-ICSSG PRU Data InputAA8
PRG1_PRU0_GPI12IPRU-ICSSG PRU Data InputU9
PRG1_PRU0_GPI13IPRU-ICSSG PRU Data InputW9
PRG1_PRU0_GPI14IPRU-ICSSG PRU Data InputAA9
PRG1_PRU0_GPI15IPRU-ICSSG PRU Data InputY9
PRG1_PRU0_GPI16IPRU-ICSSG PRU Data InputV9
PRG1_PRU0_GPI17IPRU-ICSSG PRU Data InputU7
PRG1_PRU0_GPI18IPRU-ICSSG PRU Data InputV7
PRG1_PRU0_GPI19IPRU-ICSSG PRU Data InputW7
PRG1_PRU0_GPO0IOPRU-ICSSG PRU Data OutputY7
PRG1_PRU0_GPO1IOPRU-ICSSG PRU Data OutputU8
PRG1_PRU0_GPO2IOPRU-ICSSG PRU Data OutputW8
PRG1_PRU0_GPO3IOPRU-ICSSG PRU Data OutputV8
PRG1_PRU0_GPO4IOPRU-ICSSG PRU Data OutputY8
PRG1_PRU0_GPO5IOPRU-ICSSG PRU Data OutputV13
PRG1_PRU0_GPO6IOPRU-ICSSG PRU Data OutputAA7
PRG1_PRU0_GPO7IOPRU-ICSSG PRU Data OutputU13
PRG1_PRU0_GPO8IOPRU-ICSSG PRU Data OutputW13
PRG1_PRU0_GPO9IOPRU-ICSSG PRU Data OutputU15
PRG1_PRU0_GPO10IOPRU-ICSSG PRU Data OutputU14
PRG1_PRU0_GPO11IOPRU-ICSSG PRU Data OutputAA8
PRG1_PRU0_GPO12IOPRU-ICSSG PRU Data OutputU9
PRG1_PRU0_GPO13IOPRU-ICSSG PRU Data OutputW9
PRG1_PRU0_GPO14IOPRU-ICSSG PRU Data OutputAA9
PRG1_PRU0_GPO15IOPRU-ICSSG PRU Data OutputY9
PRG1_PRU0_GPO16IOPRU-ICSSG PRU Data OutputV9
PRG1_PRU0_GPO17IOPRU-ICSSG PRU Data OutputU7
PRG1_PRU0_GPO18IOPRU-ICSSG PRU Data OutputV7
PRG1_PRU0_GPO19IOPRU-ICSSG PRU Data OutputW7
PRG1_PRU1_GPI0IPRU-ICSSG PRU Data InputW11
PRG1_PRU1_GPI1IPRU-ICSSG PRU Data InputV11
PRG1_PRU1_GPI2IPRU-ICSSG PRU Data InputAA12
PRG1_PRU1_GPI3IPRU-ICSSG PRU Data InputY12
PRG1_PRU1_GPI4IPRU-ICSSG PRU Data InputW12
PRG1_PRU1_GPI5IPRU-ICSSG PRU Data InputAA13
PRG1_PRU1_GPI6IPRU-ICSSG PRU Data InputU11
PRG1_PRU1_GPI7IPRU-ICSSG PRU Data InputV15
PRG1_PRU1_GPI8IPRU-ICSSG PRU Data InputU12
PRG1_PRU1_GPI9IPRU-ICSSG PRU Data InputV14
PRG1_PRU1_GPI10IPRU-ICSSG PRU Data InputW14
PRG1_PRU1_GPI11IPRU-ICSSG PRU Data InputAA10
PRG1_PRU1_GPI12IPRU-ICSSG PRU Data InputV10
PRG1_PRU1_GPI13IPRU-ICSSG PRU Data InputU10
PRG1_PRU1_GPI14IPRU-ICSSG PRU Data InputAA11
PRG1_PRU1_GPI15IPRU-ICSSG PRU Data InputY11
PRG1_PRU1_GPI16IPRU-ICSSG PRU Data InputY10
PRG1_PRU1_GPI17IPRU-ICSSG PRU Data InputAA14
PRG1_PRU1_GPI18IPRU-ICSSG PRU Data InputY13
PRG1_PRU1_GPI19IPRU-ICSSG PRU Data InputV12
PRG1_PRU1_GPO0IOPRU-ICSSG PRU Data OutputW11
PRG1_PRU1_GPO1IOPRU-ICSSG PRU Data OutputV11
PRG1_PRU1_GPO2IOPRU-ICSSG PRU Data OutputAA12
PRG1_PRU1_GPO3IOPRU-ICSSG PRU Data OutputY12
PRG1_PRU1_GPO4IOPRU-ICSSG PRU Data OutputW12
PRG1_PRU1_GPO5IOPRU-ICSSG PRU Data OutputAA13
PRG1_PRU1_GPO6IOPRU-ICSSG PRU Data OutputU11
PRG1_PRU1_GPO7IOPRU-ICSSG PRU Data OutputV15
PRG1_PRU1_GPO8IOPRU-ICSSG PRU Data OutputU12
PRG1_PRU1_GPO9IOPRU-ICSSG PRU Data OutputV14
PRG1_PRU1_GPO10IOPRU-ICSSG PRU Data OutputW14
PRG1_PRU1_GPO11IOPRU-ICSSG PRU Data OutputAA10
PRG1_PRU1_GPO12IOPRU-ICSSG PRU Data OutputV10
PRG1_PRU1_GPO13IOPRU-ICSSG PRU Data OutputU10
PRG1_PRU1_GPO14IOPRU-ICSSG PRU Data OutputAA11
PRG1_PRU1_GPO15IOPRU-ICSSG PRU Data OutputY11
PRG1_PRU1_GPO16IOPRU-ICSSG PRU Data OutputY10
PRG1_PRU1_GPO17IOPRU-ICSSG PRU Data OutputAA14
PRG1_PRU1_GPO18IOPRU-ICSSG PRU Data OutputY13
PRG1_PRU1_GPO19IOPRU-ICSSG PRU Data OutputV12
PRG1_PWM0_TZ_INIPRU_ICSSG PWM Trip Zone InputV7
PRG1_PWM0_TZ_OUTOPRU_ICSSG PWM Trip Zone OutputW7
PRG1_PWM1_TZ_INIPRU_ICSSG PWM Trip Zone InputY13
PRG1_PWM1_TZ_OUTOPRU_ICSSG PWM Trip Zone OutputV12
PRG1_PWM2_TZ_INIPRU_ICSSG PWM Trip Zone InputP19, W14
PRG1_PWM2_TZ_OUTOPRU_ICSSG PWM Trip Zone OutputR20, U12
PRG1_PWM3_TZ_INIPRU_ICSSG PWM Trip Zone InputU15
PRG1_PWM3_TZ_OUTOPRU_ICSSG PWM Trip Zone OutputAA8
PRG1_PWM0_A0IOPRU_ICSSG PWM Output AU9
PRG1_PWM0_A1IOPRU_ICSSG PWM Output AAA9
PRG1_PWM0_A2IOPRU_ICSSG PWM Output AV9
PRG1_PWM0_B0IOPRU_ICSSG PWM Output BW9
PRG1_PWM0_B1IOPRU_ICSSG PWM Output BY9
PRG1_PWM0_B2IOPRU_ICSSG PWM Output BU7
PRG1_PWM1_A0IOPRU_ICSSG PWM Output AV10
PRG1_PWM1_A1IOPRU_ICSSG PWM Output AAA11
PRG1_PWM1_A2IOPRU_ICSSG PWM Output AY10
PRG1_PWM1_B0IOPRU_ICSSG PWM Output BU10
PRG1_PWM1_B1IOPRU_ICSSG PWM Output BY11
PRG1_PWM1_B2IOPRU_ICSSG PWM Output BAA14
PRG1_PWM2_A0IOPRU_ICSSG PWM Output AN16, W8
PRG1_PWM2_A1IOPRU_ICSSG PWM Output AP17, W13
PRG1_PWM2_A2IOPRU_ICSSG PWM Output AAA12, V21
PRG1_PWM2_B0IOPRU_ICSSG PWM Output BN17, Y8
PRG1_PWM2_B1IOPRU_ICSSG PWM Output BU14, Y18
PRG1_PWM2_B2IOPRU_ICSSG PWM Output BR16, W12
PRG1_PWM3_A0IOPRU_ICSSG PWM Output AY7
PRG1_PWM3_A1IOPRU_ICSSG PWM Output AAA7
PRG1_PWM3_A2IOPRU_ICSSG PWM Output AV8
PRG1_PWM3_B0IOPRU_ICSSG PWM Output BU8
PRG1_PWM3_B1IOPRU_ICSSG PWM Output BU13
PRG1_PWM3_B2IOPRU_ICSSG PWM Output BV13
PRG1_RGMII1_RXCIPRU_ICSSG RGMII Receive ClockAA7
PRG1_RGMII1_RX_CTLIPRU_ICSSG RGMII Receive ControlY8
PRG1_RGMII1_TXCIOPRU_ICSSG RGMII Transmit ClockV9
PRG1_RGMII1_TX_CTLOPRU_ICSSG RGMII Transmit ControlY9
PRG1_RGMII2_RXCIPRU_ICSSG RGMII Receive ClockU11
PRG1_RGMII2_RX_CTLIPRU_ICSSG RGMII Receive ControlW12
PRG1_RGMII2_TXCIOPRU_ICSSG RGMII Transmit ClockY10
PRG1_RGMII2_TX_CTLOPRU_ICSSG RGMII Transmit ControlY11
PRG1_RGMII1_RD0IPRU_ICSSG RGMII Receive DataY7
PRG1_RGMII1_RD1IPRU_ICSSG RGMII Receive DataU8
PRG1_RGMII1_RD2IPRU_ICSSG RGMII Receive DataW8
PRG1_RGMII1_RD3IPRU_ICSSG RGMII Receive DataV8
PRG1_RGMII1_TD0OPRU_ICSSG RGMII Transmit DataAA8
PRG1_RGMII1_TD1OPRU_ICSSG RGMII Transmit DataU9
PRG1_RGMII1_TD2OPRU_ICSSG RGMII Transmit DataW9
PRG1_RGMII1_TD3OPRU_ICSSG RGMII Transmit DataAA9
PRG1_RGMII2_RD0IPRU_ICSSG RGMII Receive DataW11
PRG1_RGMII2_RD1IPRU_ICSSG RGMII Receive DataV11
PRG1_RGMII2_RD2IPRU_ICSSG RGMII Receive DataAA12
PRG1_RGMII2_RD3IPRU_ICSSG RGMII Receive DataY12
PRG1_RGMII2_TD0OPRU_ICSSG RGMII Transmit DataAA10
PRG1_RGMII2_TD1OPRU_ICSSG RGMII Transmit DataV10
PRG1_RGMII2_TD2OPRU_ICSSG RGMII Transmit DataU10
PRG1_RGMII2_TD3OPRU_ICSSG RGMII Transmit DataAA11
PRG1_UART0_CTSnIPRU-ICSSG UART Clear to Send (active low)U15
PRG1_UART0_RTSnOPRU-ICSSG UART Request to Send (active low)U14
PRG1_UART0_RXDIPRU-ICSSG UART Receive DataV14
PRG1_UART0_TXDOPRU-ICSSG UART Transmit DataW14