6.9.3.1 Reset Timing

Tables and figures provided in this section define timing conditions, timing requirements, and switching characteristics for reset related signals.

Table 6-6 Reset Timing Conditions

PARAMETER			MIN	MAX	UNIT
INPUT CONDITIONS
SR_I	Input slew rate	VDD⁽¹⁾ = 1.8V	0.0018		V/ns
SR_I	Input slew rate	VDD⁽¹⁾ = 3.3V	0.0033		V/ns
OUTPUT CONDITIONS
C_L	Output load capacitance			30	pF

(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see POWER column of the Pin Attributes table.

Table 6-7 MCU_PORz Timing Requirements see Figure 6-7

NO.	PARAMETER		MIN	UNIT
RST1	t_{h(SUPPLIES_VALID - MCU_PORz)}	Hold time, MCU_PORz active (low) at Power-up after supplies valid (using external crystal circuit)	9500000	ns
RST2	t_{h(SUPPLIES_VALID - MCU_PORz)}	Hold time, MCU_PORz active (low) at Power-up after supplies valid and external clock stable (using external LVCMOS clock source)	1200	ns
RST3	t_{w(MCU_PORzL)}	Pulse Width, MCU_PORz low after Power-up (without removal of Power or system reference clock MCU_OSC0_XI/XO)	1200	ns

Figure 6-7 MCU_PORz Timing Requirements

Table 6-8 MCU_RESETSTATz, and RESETSTATz Switching Characteristics see Figure 6-8

NO.	PARAMETER		MIN	UNIT
RST4	t_{d(MCU_PORzL-MCU_RESETSTATzL)}	Delay time, MCU_PORz active (low) to MCU_RESETSTATz active (low)	0	ns
RST5	t_{d(MCU_PORzH-MCU_RESETSTATzH)}	Delay time, MCU_PORz inactive (high) to MCU_RESETSTATz inactive (high)	6120*S⁽¹⁾	ns
RST6	t_{d(MCU_PORzL-RESETSTATzL)}	Delay time, MCU_PORz active (low) to RESETSTATz active (low)	0	ns
RST7	t_{d(MCU_PORzH-RESETSTATzH)}	Delay time, MCU_PORz inactive (high) to RESETSTATz inactive (high)	9195*S⁽¹⁾	ns
RST8	t_{w(MCU_RESETSTATzL)}	Pulse Width, MCU_RESETSTATz low (SW_MCU_WARMRST)	966*S⁽¹⁾	ns
RST9	t_{w(RESETSTATzL)}	Pulse Width, RESETSTATz low (SW_MCU_WARMRST, SW_MAIN_PORz, or SW_MAIN_WARMRST)	4040*S	ns

(1) S = MCU_OSC0_XI/XO clock period in ns.

AM67 AM67A MCU_RESETSTATz, and RESETSTATz Switching Characteristics

Figure 6-8 MCU_RESETSTATz, and RESETSTATz Switching Characteristics

Table 6-9 MCU_RESETz Timing Requirements see Figure 6-9

NO.	PARAMETER		MIN	MAX	UNIT
RST10	t_{w(MCU_RESETzL)}⁽¹⁾	Pulse Width, MCU_RESETz active (low)	1200		ns

(1) This timing parameter is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.

Table 6-10 MCU_RESETSTATz, and RESETSTATz Switching Characteristics see Figure 6-9

NO.	PARAMETER		MIN	UNIT
RST11	t_{d(MCU_RESETzL-MCU_RESETSTATzL)}	Delay time, MCU_RESETz active (low) to MCU_RESETSTATz active (low)	0	ns
RST12	t_{d(MCU_RESETzH-MCU_RESETSTATzH)}	Delay time, MCU_RESETz inactive (high) to MCU_RESETSTATz inactive (high)	966*S⁽¹⁾	ns
RST13	t_{d(MCU_RESETzL-RESETSTATzL)}	Delay time, MCU_RESETz active (low) to RESETSTATz active (low)	960	ns
RST14	t_{d(MCU_RESETzH-RESETSTATzH)}	Delay time, MCU_RESETz inactive (high) to RESETSTATz inactive (high)	4040*S⁽¹⁾	ns

(1) S = MCU_OSC0_XI/XO clock period in ns.

AM67 AM67A MCU_RESETz, MCU_RESETSTATz, and RESETSTATz Timing Requirements and Switching Characteristics

Figure 6-9 MCU_RESETz, MCU_RESETSTATz, and RESETSTATz Timing Requirements and Switching Characteristics

Table 6-11 RESET_REQz Timing Requirements see Figure 6-10

NO.	PARAMETER		MIN	MAX	UNIT
RST15	t_{w(RESET_REQzL)}⁽¹⁾	Pulse Width, RESET_REQz active (low)	1200		ns

(1) This timing parameter is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.

Table 6-12 RESETSTATz Switching Characteristics see Figure 6-10

NO.	PARAMETER		MIN	MAX	UNIT
RST16	t_{d(RESET_REQzL-RESETSTATzL)}	Delay time, RESET_REQz active (low) to RESETSTATz active (low)	900*T⁽¹⁾		ns
RST17	t_{d(RESET_REQzH-RESETSTATzH)}	Delay time, RESET_REQz inactive (high) to RESETSTATz inactive (high)	4040*S⁽²⁾		ns

(1) T = Reset Isolation Time (Software Dependent)

(2) S = MCU_OSC0_XI/XO clock period in ns.

AM67 AM67A RESET_REQz and RESETSTATz Timing Requirements and Switching Characteristics

Figure 6-10 RESET_REQz and RESETSTATz Timing Requirements and Switching Characteristics

Table 6-13 EMUx Timing Requirements see Figure 6-11

NO.	PARAMETER		MIN	MAX	UNIT
RST18	t_{su(EMUx-MCU_PORz)}	Setup time, EMU[1:0] before MCU_PORz inactive (high)	3*S⁽¹⁾		ns
RST19	t_{h(MCU_PORz - EMUx)}	Hold time, EMU[1:0] after MCU_PORz inactive (high)	10		ns

(1) S = MCU_OSC0_XI/XO clock period in ns.

Figure 6-11 EMUx Timing Requirements

Table 6-14 BOOTMODE Timing Requirements see Figure 6-12

NO.	PARAMETER		MIN	MAX	UNIT
RST23	t_{su(BOOTMODE-PORz_OUT)}	Setup time, BOOTMODE[15:00] valid before PORz_OUT high (External MCU PORz event or Software SW_MAIN_PORz)	3*S⁽¹⁾		ns
RST24	t_{h(PORz_OUT - BOOTMODE)}	Hold time, BOOTMODE[15:00] valid after PORz_OUT high (External MCU PORz event, or Software SW_MAIN_PORz)	0		ns

(1) S = MCU_OSC0_XI/XO clock period in ns.

Table 6-15 PORz_OUT Switching Characteristics see Figure 6-12

NO.	PARAMETER		MIN	UNIT
RST25	t_{d(MCU_PORzL-PORz_OUT)}	Delay time, MCU_PORz active (low) to PORz_OUT active (low)	0	ns
RST26	t_{d(MCU_PORzH-PORz_OUT)}	Delay time, MCU_PORz inactive (high) to PORz_OUT inactive (high)	1840	ns
RST27	t_{w(PORz_OUTL)}	Pulse Width, PORz_OUT low (MCU_PORz or SW_MAIN_PORz)	1200	ns

AM67 AM67A BOOTMODE Timing Requirements and PORz_OUT Switching Characteristics

Figure 6-12 BOOTMODE Timing Requirements and PORz_OUT Switching Characteristics