SPRSP91A february   2023  – august 2023 AM68 , AM68A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      11
      2.      12
    3. 6.3 Signal Descriptions
      1.      14
      2. 6.3.1  ADC
        1. 6.3.1.1 MCU Domain
          1.        17
          2.        18
          3.        19
      3. 6.3.2  DDRSS
        1. 6.3.2.1 MAIN Domain
          1.        22
          2.        23
      4. 6.3.3  GPIO
        1. 6.3.3.1 MAIN Domain
          1.        26
        2. 6.3.3.2 WKUP Domain
          1.        28
      5. 6.3.4  I2C
        1. 6.3.4.1 MAIN Domain
          1.        31
          2.        32
          3.        33
          4.        34
          5.        35
          6.        36
          7.        37
        2. 6.3.4.2 MCU Domain
          1.        39
          2.        40
        3. 6.3.4.3 WKUP Domain
          1.        42
      6. 6.3.5  I3C
        1. 6.3.5.1 MCU Domain
          1.        45
      7. 6.3.6  MCAN
        1. 6.3.6.1 MAIN Domain
          1.        48
          2.        49
          3.        50
          4.        51
          5.        52
          6.        53
          7.        54
          8.        55
          9.        56
          10.        57
          11.        58
          12.        59
          13.        60
          14.        61
          15.        62
          16.        63
          17.        64
          18.        65
        2. 6.3.6.2 MCU Domain
          1.        67
          2.        68
      8. 6.3.7  MCSPI
        1. 6.3.7.1 MAIN Domain
          1.        71
          2.        72
          3.        73
          4.        74
          5.        75
          6.        76
          7.        77
        2. 6.3.7.2 MCU Domain
          1.        79
          2.        80
      9. 6.3.8  UART
        1. 6.3.8.1 MAIN Domain
          1.        83
          2.        84
          3.        85
          4.        86
          5.        87
          6.        88
          7.        89
          8.        90
          9.        91
          10.        92
        2. 6.3.8.2 MCU Domain
          1.        94
        3. 6.3.8.3 WKUP Domain
          1.        96
      10. 6.3.9  MDIO
        1. 6.3.9.1 MAIN Domain
          1.        99
        2. 6.3.9.2 MCU Domain
          1.        101
      11. 6.3.10 CPSW2G
        1. 6.3.10.1 MAIN Domain
          1.        104
        2. 6.3.10.2 MCU Domain
          1.        106
      12. 6.3.11 ECAP
        1. 6.3.11.1 MAIN Domain
          1.        109
          2.        110
          3.        111
      13. 6.3.12 EQEP
        1. 6.3.12.1 MAIN Domain
          1.        114
          2.        115
          3.        116
      14. 6.3.13 EPWM
        1. 6.3.13.1 MAIN Domain
          1.        119
          2.        120
          3.        121
          4.        122
          5.        123
          6.        124
          7.        125
      15. 6.3.14 USB
        1. 6.3.14.1 MAIN Domain
          1.        128
      16. 6.3.15 Display Port
        1. 6.3.15.1 MAIN Domain
          1.        131
      17. 6.3.16 Hyperlink
        1. 6.3.16.1 MAIN Domain
          1.        134
          2.        135
          3.        136
      18. 6.3.17 PCIE
        1. 6.3.17.1 MAIN Domain
          1.        139
      19. 6.3.18 SERDES
        1. 6.3.18.1 MAIN Domain
          1.        142
      20. 6.3.19 DSI
        1. 6.3.19.1 MAIN Domain
          1.        145
          2.        146
      21. 6.3.20 CSI
        1. 6.3.20.1 MAIN Domain
          1.        149
          2.        150
      22. 6.3.21 MCASP
        1. 6.3.21.1 MAIN Domain
          1.        153
          2.        154
          3.        155
          4.        156
          5.        157
      23. 6.3.22 DMTIMER
        1. 6.3.22.1 MAIN Domain
          1.        160
        2. 6.3.22.2 MCU Domain
          1.        162
      24. 6.3.23 CPTS
        1. 6.3.23.1 MAIN Domain
          1.        165
        2. 6.3.23.2 MCU Domain
          1.        167
      25. 6.3.24 DSS
        1. 6.3.24.1 MAIN Domain
          1.        170
      26. 6.3.25 GPMC
        1. 6.3.25.1 MAIN Domain
          1.        173
      27. 6.3.26 MMC
        1. 6.3.26.1 MAIN Domain
          1.        176
          2.        177
      28. 6.3.27 OSPI
        1. 6.3.27.1 MCU Domain
          1.        180
          2.        181
      29. 6.3.28 Hyperbus
        1. 6.3.28.1 MCU Domain
          1.        184
      30. 6.3.29 Emulation and Debug
        1. 6.3.29.1 MAIN Domain
          1.        187
          2.        188
      31. 6.3.30 System and Miscellaneous
        1. 6.3.30.1 Boot Mode configuration
          1.        191
        2. 6.3.30.2 Clock
          1.        193
          2.        194
        3. 6.3.30.3 System
          1.        196
          2.        197
        4. 6.3.30.4 EFUSE
          1.        199
        5. 6.3.30.5 VMON
          1.        201
      32. 6.3.31 Power
        1.       203
    4. 6.4 Connection for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Power-On-Hour (POH) Limits
    5. 7.5  Operating Performance Points
    6. 7.6  Electrical Characteristics
      1. 7.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 7.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 7.6.3  HFOSC/LFOSC Electrical Characteristics
      4. 7.6.4  eMMCPHY Electrical Characteristics
      5. 7.6.5  SDIO Electrical Characteristics
      6. 7.6.6  CSI2/DSI D-PHY Electrical Characteristics
      7. 7.6.7  ADC12B Electrical Characteristics
      8. 7.6.8  LVCMOS Electrical Characteristics
      9. 7.6.9  USB2PHY Electrical Characteristics
      10. 7.6.10 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics
      11. 7.6.11 UFS M-PHY Electrical Characteristics
      12. 7.6.12 eDP/DP AUX-PHY Electrical Characteristics
      13. 7.6.13 DDR0 Electrical Characteristics
    7. 7.7  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.7.2 Hardware Requirements
      3. 7.7.3 Programming Sequence
      4. 7.7.4 Impact to Your Hardware Warranty
    8. 7.8  Thermal Resistance Characteristics
      1. 7.8.1 Thermal Resistance Characteristics for ALZ Package
    9. 7.9  Temperature Sensor Characteristics
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1 Timing Parameters and Information
      2. 7.10.2 Power Supply Sequencing
        1. 7.10.2.1 Power Supply Slew Rate Requirement
        2. 7.10.2.2 Combined MCU and Main Domains Power- Up Sequencing
        3. 7.10.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 7.10.2.4 Isolated MCU and Main Domains Power- Up Sequencing
        5. 7.10.2.5 Isolated MCU and Main Domains Power- Down Sequencing
        6. 7.10.2.6 Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
        7. 7.10.2.7 Independent MCU and Main Domains, Entry and Exit of DDR Retention State
        8. 7.10.2.8 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
      3. 7.10.3 System Timing
        1. 7.10.3.1 Reset Timing
        2. 7.10.3.2 Safety Signal Timing
        3. 7.10.3.3 Clock Timing
      4. 7.10.4 Clock Specifications
        1. 7.10.4.1 Input and Output Clocks / Oscillators
          1. 7.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 7.10.4.1.1.1 Load Capacitance
            2. 7.10.4.1.1.2 Shunt Capacitance
          2. 7.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 7.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 7.10.4.1.3.1 Load Capacitance
            2. 7.10.4.1.3.2 Shunt Capacitance
          4. 7.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 7.10.4.1.5 Auxiliary OSC1 Not Used
        2. 7.10.4.2 Output Clocks
        3. 7.10.4.3 PLLs
        4. 7.10.4.4 Module and Peripheral Clocks Frequencies
      5. 7.10.5 Peripherals
        1. 7.10.5.1  ATL
          1. 7.10.5.1.1 ATL_PCLK Timing Requirements
          2. 7.10.5.1.2 ATL_AWS[x] Timing Requirements
          3. 7.10.5.1.3 ATL_BWS[x] Timing Requirements
          4. 7.10.5.1.4 ATCLK[x] Switching Characteristics
        2. 7.10.5.2  CPSW2G
          1. 7.10.5.2.1 CPSW2G MDIO Interface Timings
          2. 7.10.5.2.2 CPSW2G RMII Timings
            1. 7.10.5.2.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 7.10.5.2.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 7.10.5.2.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 7.10.5.2.3 CPSW2G RGMII Timings
            1. 7.10.5.2.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 7.10.5.2.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 7.10.5.2.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 7.10.5.2.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        3. 7.10.5.3  CSI-2
        4. 7.10.5.4  DDRSS
        5. 7.10.5.5  DSS
        6. 7.10.5.6  eCAP
          1. 7.10.5.6.1 Timing Requirements for eCAP
          2. 7.10.5.6.2 Switching Characteristics for eCAP
        7. 7.10.5.7  EPWM
          1. 7.10.5.7.1 Timing Requirements for eHRPWM
          2. 7.10.5.7.2 Switching Characteristics for eHRPWM
        8. 7.10.5.8  eQEP
          1. 7.10.5.8.1 Timing Requirements for eQEP
          2. 7.10.5.8.2 Switching Characteristics for eQEP
        9. 7.10.5.9  GPIO
          1. 7.10.5.9.1 GPIO Timing Requirements
          2. 7.10.5.9.2 GPIO Switching Characteristics
        10. 7.10.5.10 GPMC
          1. 7.10.5.10.1 GPMC and NOR Flash — Synchronous Mode
            1. 7.10.5.10.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 7.10.5.10.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 7.10.5.10.2 GPMC and NOR Flash — Asynchronous Mode
            1. 7.10.5.10.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.10.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 7.10.5.10.3 GPMC and NAND Flash — Asynchronous Mode
            1. 7.10.5.10.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.10.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
          4. 7.10.5.10.4 GPMC0 IOSET
        11. 7.10.5.11 HyperBus
          1. 7.10.5.11.1 Timing Requirements for HyperBus
          2. 7.10.5.11.2 HyperBus 166 MHz Switching Characteristics
          3. 7.10.5.11.3 HyperBus 100 MHz Switching Characteristics
        12. 7.10.5.12 I2C
        13. 7.10.5.13 I3C
        14. 7.10.5.14 MCAN
        15. 7.10.5.15 MCASP
        16. 7.10.5.16 MCSPI
          1. 7.10.5.16.1 MCSPI — Controller Mode
          2. 7.10.5.16.2 MCSPI — Peripheral Mode
        17. 7.10.5.17 MMCSD
          1. 7.10.5.17.1 MMC0 - eMMC Interface
            1. 7.10.5.17.1.1 Legacy SDR Mode
            2. 7.10.5.17.1.2 High Speed SDR Mode
            3. 7.10.5.17.1.3 High Speed DDR Mode
            4. 7.10.5.17.1.4 HS200 Mode
            5. 7.10.5.17.1.5 HS400 Mode
          2. 7.10.5.17.2 MMC1/2 - SD/SDIO Interface
            1. 7.10.5.17.2.1 Default Speed Mode
            2. 7.10.5.17.2.2 High Speed Mode
            3. 7.10.5.17.2.3 UHS–I SDR12 Mode
            4. 7.10.5.17.2.4 UHS–I SDR25 Mode
            5. 7.10.5.17.2.5 UHS–I SDR50 Mode
            6. 7.10.5.17.2.6 UHS–I DDR50 Mode
            7. 7.10.5.17.2.7 UHS–I SDR104 Mode
        18. 7.10.5.18 CPTS
          1. 7.10.5.18.1 CPTS Timing Requirements
          2. 7.10.5.18.2 CPTS Switching Characteristics
        19. 7.10.5.19 OSPI
          1. 7.10.5.19.1 OSPI0 PHY Mode
            1. 7.10.5.19.1.1 OSPI With Data Training
              1. 7.10.5.19.1.1.1 OSPI Switching Characteristics – Data Training
            2. 7.10.5.19.1.2 OSPI Without Data Training
              1. 7.10.5.19.1.2.1 OSPI Timing Requirements – SDR Mode
              2. 7.10.5.19.1.2.2 OSPI Switching Characteristics – SDR Mode
              3. 7.10.5.19.1.2.3 OSPI Timing Requirements – DDR Mode
              4. 7.10.5.19.1.2.4 OSPI Switching Characteristics – DDR Mode
          2. 7.10.5.19.2 OSPI0 Tap Mode
            1. 7.10.5.19.2.1 OSPI0 Tap SDR Timing
            2. 7.10.5.19.2.2 OSPI0 Tap DDR Timing
        20. 7.10.5.20 PCIE
        21. 7.10.5.21 Timers
          1. 7.10.5.21.1 Timing Requirements for Timers
          2. 7.10.5.21.2 Switching Characteristics for Timers
        22. 7.10.5.22 UART
          1. 7.10.5.22.1 Timing Requirements for UART
          2. 7.10.5.22.2 UART Switching Characteristics
        23. 7.10.5.23 USB
      6. 7.10.6 Emulation and Debug
        1. 7.10.6.1 Trace
        2. 7.10.6.2 JTAG
          1. 7.10.6.2.1 JTAG Electrical Data and Timing
            1. 7.10.6.2.1.1 JTAG Timing Requirements
            2. 7.10.6.2.1.2 JTAG Switching Characteristics
  9. 8 Detailed Description
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Device Connection and Layout Fundamentals
      1. 9.1.1 Power Supply Decoupling and Bulk Capacitors
        1. 9.1.1.1 Power Distribution Network Implementation Guidance
      2. 9.1.2 External Oscillator
      3. 9.1.3 JTAG and EMU
      4. 9.1.4 Reset
      5. 9.1.5 Unused Pins
      6. 9.1.6 Hardware Design Guide for JacintoTM 7 Devices
    2. 9.2 Peripheral- and Interface-Specific Design Information
      1. 9.2.1 LPDDR4 Board Design and Layout Guidelines
      2. 9.2.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 9.2.2.1 No Loopback and Internal Pad Loopback
        2. 9.2.2.2 External Board Loopback
        3. 9.2.2.3 DQS (only available in Octal Flash devices)
      3. 9.2.3 USB VBUS Design Guidelines
      4. 9.2.4 System Power Supply Monitor Design Guidelines using VMON/POK
      5. 9.2.5 High Speed Differential Signal Routing Guidance
      6. 9.2.6 Thermal Solution Guidance
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Trademarks
    5. 10.5 Support Resources
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALZ|770
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.10.3.1 Reset Timing

The tables and figures provided in this section define the timing requirements and switching characteristics for reset related signals.

Table 7-6 MCU_PORz Timing Requirements see Figure 7-10
NO. MINTYPMAXUNIT
RST1th(MCUD_SUPPLIES_VALID - MCU_PORz)Hold time, MCU_PORz active (low) at Power-up after all MCU DOMAIN supplies valid (using external crystal)N + 1200(2)9500000ns
RST2Hold time, MCU_PORz active (low) at Power-up after all MCU DOMAIN supplies(1) valid and external clock stable (using external LVCMOS oscillator)1200ns
RST3tw(MCU_PORzL)Pulse Width minimum, MCU_PORz low after Power-up (without removal of Power or system reference clock MCU_OSC0_XI/XO)1200ns
(1) For the definition of the MCU DOMAIN supplies, see the Section 7.10.2.2, Combined MCU and Main Domains Poewr-Up Sequencing.
(2) N = oscillator start-up time
GUID-7860E5A6-0922-4B61-A4ED-9FD5F00A6211-low.gifFigure 7-10 MCU_PORz Timing Requirements
Table 7-7 PORz Timing Requirements see Figure 7-11
NO.MINMAXUNIT
RST4th(MAIND_SUPPLIES_VALID - PORz)Hold time, PORz active (low) at Power-up after all MAIN DOMAIN supplies(1) valid1200ns
RST5tw(PORzL)Pulse Width minimum, PORz low after Power-up1200ns
(1) For the definition of the MAIN DOMAIN supplies, see the Section 7.10.2.2, Combined MCU and Main Domains Poewr-Up Sequencing.
GUID-D364E3FC-4947-44C6-B35B-2FCFF6CFA080-low.gifFigure 7-11 PORz Timing Requirements
Table 7-8 MCU_PORz initiates; MCU_PORz_OUT, PORz_OUT, MCU_RESETSTATz, and RESETSTATz Switching Characteristics see Figure 7-12
NO.PARAMETERMODEMINMAXUNIT
RST6td(MCU_PORzL-MCU_PORz_OUTL)Delay time, MCU_PORz active (low) to MCU_PORz_OUT active (low)0ns
RST7td(MCU_PORzH-MCU_PORz_OUTH)Delay time, MCU_PORz inactive (high) to MCU_PORz_OUT inactive (high)0ns
RST8td(MCU_PORzL-PORz_OUTL)Delay time, MCU_PORz active (low) to PORz_OUT active (low)0ns
RST9td(MCU_PORzH-PORz_OUTH)Delay time, MCU_PORz inactive (high) to PORz_OUT inactive (high)1500ns
RST10td(MCU_PORzL-MCU_RESETSTATzL)Delay time, MCU_PORz active (low) to MCU_RESETSTATz active (low)0ns
RST11td(MCU_PORzH-MCU_RESETSTATzH)Delay time, MCU_PORz inactive (high) to MCU_RESETSTATz inactive (high)POST
bypass		12000*S(1)ns
RST12td(MCU_PORzL-RESETSTATzL)Delay time, MCU_PORz active (low) to RESETSTATz active (low)0ns
RST13td(MCU_PORzH-RESETSTATzH)Delay time, MCU_PORz inactive (high) to RESETSTATz inactive (high)14500*S(1)ns
RST14tw(MCU_PORz_OUTL)Pulse width minimum, MCU_PORz_OUT active (low)1200ns
RST15tw(PORz_OUTL)Pulse Width Minimum PORz_OUT low2550ns
RST16tw(MCU_RESETSTATzL)Pulse Width Minimum MCU_RESETSTATz low3900*S(1)ns
RST17tw(RESETSTATzL)Pulse Width Minimum RESETSTATz low2650*S(1)ns
(1) S = MCU_OSC0_XI/XO clock period.
GUID-E53BEE91-6514-4674-A52A-295C6124E850-low.gifFigure 7-12 MCU_PORz initiates; MCU_PORz_OUT, PORz_OUT, MCU_RESETSTATz, and RESETSTATz Switching Characteristics
Table 7-9 PORz Initiates; PORz_OUT and RESETSTATz Switching Characteristics see Figure 7-13
NO.PARAMETERMODEMINMAXUNIT
RST18td(PORzL-PORz_OUTL)Delay time, PORz active (low) toPORz_OUT active (low)software control of
POR_RST_ISO_DONE_Z		T(1)  
CTRLMMR_WKUP_POR_RST
_CTRL[0].POR_RST_ISO_
DONE_Z = 0		0ns
RST19td(PORzH-PORz_OUTH)Delay time, PORz active (high) toPORz_OUT active (high)1300  ns
RST20td(PORzL-RESETSTATzL)Delay time, PORz active (low) to RESETSTATz active (low)T(1)  
CTRLMMR_WKUP_POR_RST
_CTRL[0].POR_RST_ISO_
DONE_Z = 0		0ns
RST21td(PORzH-RESETSTATzH)Delay time, PORz active (high) to RESETSTATz active (high)14500*S(2)  ns
(1) T = Reset Isolation Time (Software Dependent).
(2) S = MCU_OSC0_XI/XO clock period.
GUID-1CFAE11A-5CEC-4C06-AC75-4D0E026484CE-low.gifFigure 7-13 PORz initiates; PORz_OUT and RESETSTATz Switching Characteristics
Table 7-10 MCU_RESETz Timing Requirements see Figure 7-14
NO.MINMAXUNIT
RST22tw(MCU_RESETzL)(1)Pulse Width minimum, MCU_RESETz active (low)1200ns
(1) Timing for MCU_RESETz is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.
Table 7-11 MCU_RESETz initiates; MCU_RESETSTATz, and RESETSTATz Switching Characteristics see Figure 7-14
NO.PARAMETERMINMAXUNIT
RST23td(MCU_RESETzL-MCU_RESETSTATzL)Delay time, MCU_RESETz active (low) to MCU_RESETSTATz active (low)800  ns
RST24td(MCU_RESETzH-MCU_RESETSTATzH)Delay time, MCU_RESETz inactive (high) to MCU_RESETSTATz inactive (high)3900*S(1)  ns
RST25td(MCU_RESETzL-RESETSTATzL)Delay time, MCU_RESETz active (low) to RESETSTATz active (low)800  ns
RST26td(MCU_RESETzH-RESETSTATzH)Delay time, MCU_RESETz inactive (high) to RESETSTATz inactive (high)3900*S(1)  ns
(1) S = MCU_OSC0_XI/XO clock period.
GUID-E92F6E05-EC11-4208-A584-776DC12640CE-low.gifFigure 7-14 MCU_RESETz initiates; MCU_RESETSTATz, and RESETSTATz Timing Requirements and Switching Characteristics
Table 7-12 RESET_REQz Timing Requirements see Figure 7-15
NO.MINMAXUNIT
RST27tw(RESET_REQzL)(1)Pulse Width minimum, RESET_REQz active (low)1200ns
(1) Timing for RESET_REQz is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.
Table 7-13 RESET_REQz initiates; RESETSTATz Switching Characteristics see Figure 7-15
NO.PARAMETERMODEMINMAXUNIT
RST28td(RESET_REQzL-RESETSTATzL)Delay time, RESET_REQz active (low) to RESETSTATz active (low)software control of
SOC_WARMRST_ISO_DONE_Z		T(1)  
CTRLMMR_WKUP_MAIN_WARM
_RST_CTRL[0].SOC_
WARMRST_ISO_DONE_Z = 0		740ns
RST29td(RESET_REQzH-RESETSTATzH)Delay time, RESET_REQz inactive (high) to RESETSTATz inactive (high)2650*S(2)  ns
(1) T = Reset Isolation Time (Software Dependent).
(2) S = MCU_OSC0_XI/XO clock period.
GUID-61722AEB-427A-4910-AC6B-6B424D42462E-low.gifFigure 7-15 RESET_REQz initiates; RESETSTATz Timing Requirements and Switching Characteristics
Table 7-14 EMUx Timing Requirements see Figure 7-16
NO. MINMAXUNIT
RST30tsu(EMUx-MCU_PORz)Setup time, EMU[1:0] before MCU_PORz inactive (high)3*S(1)ns
RST31th(MCU_PORz - EMUx)Hold time, EMU[1:0] after MCU_PORz inactive (high)10ns
(1) S = MCU_OSC0_XI/XO clock period.
GUID-44E3A670-876D-47C1-8F2E-380E2B173380-low.gifFigure 7-16 EMUx Timing Requirements
Table 7-15 MCU_BOOTMODE Timing Requirements see Figure 7-17
NO.MINMAXUNIT
RST32tsu(MCU_BOOTMODE-MCU_PORz_OUT)Setup time, MCU_BOOTMODE[09:00] before MCU_PORz_OUT high3*S(1)ns
RST33th(MCU_PORz_OUT - MCU_BOOTMODE)Hold time, MCU_BOOTMODE[09:00] after MCU_ PORz_OUT high0ns
(1) S = MCU_OSC0_XI/XO clock period.
GUID-5B8BF90D-389D-4C7A-8AF7-CCD8FF55E7AA-low.gifFigure 7-17 MCU_BOOTMODE Timing Requirements
Table 7-16 BOOTMODE Timing Requirements see Figure 7-18
NO. MINMAXUNIT
RST34tsu(BOOTMODE-PORz_OUT)Setup time, BOOTMODE[7:0] before PORz_OUT high3*S(1)  ns
RST35th(PORz_OUT - BOOTMODE)Hold time, BOOTMODE[7:0] after PORz_OUT high0  ns
(1) S = MCU_OSC0_XI/XO clock period.
GUID-E74FFB2E-2A22-4A7A-B4EF-E8678E240E0F-low.gifFigure 7-18 BOOTMODE Timing Requirements