SPRSP91A february 2023 – august 2023 AM68 , AM68A
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Table 7-51, Figure 7-73, Table 7-52, and Figure 7-76 present timing requirements and switching characteristics for MCSPI – Controller Mode.
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
SM4 | tsu(misoV-spiclkV) | Setup time, SPI_D[x] valid before SPI_CLK active edge | 2.9 | ns | |
SM5 | th(spiclkV-misoV) | Hold time, SPI_D[x] valid after SPI_CLK active edge | 2 | ns |
NO. | PARAMETER | MODE | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
SM1 | tc(spiclk) | Cycle time, SPI_CLK | 20.8 | ns | ||
SM2 | tw(spiclkL) | Pulse duration, SPI_CLK low | 0.5P - 1(1) | ns | ||
SM3 | tw(spiclkH) | Pulse duration, SPI_CLK high | 0.5P - 1(1) | ns | ||
SM6 | td(spiclkV-simoV) | Delay time, SPI_CLK active edge to SPI_D[x] transition | –2 | 2 | ns | |
SM7 | td(csV-simoV) | Delay time, SPI_CSi active edge to SPI_D[x] transition | 5 | ns | ||
SM8 | td(csV-spiclk) | Delay time, SPI_CSi active to SPI_CLK first edge | PHA = 0(2) | B - 4(3) | ns | |
PHA = 1 (2) | A - 4(4) | ns | ||||
SM9 | td(spiclkV-csV) | Delay time, SPI_CLK last edge to SPI_CSi inactive | PHA = 0(2) | A - 4(4) | ns | |
PHA = 1(2) | B - 4(3) | ns |