4 Revision History
Changes from March 2, 2023 to August 18, 2023 (from Revision * (March 2023) to Revision A (August 2023))
-
Global: Updated/Changed document title from
"AM68Ax" to "AM68x"Go
-
Global:: Deleted all OLDI/LVDS content; n/a
to this device suiteGo
-
Global: Updated/Changed "BSX",
"BSX-64-4", and "BXS-64-4" to "IMG
BXS-4-64" for the 3D Graphics Processing Unit
(GPU)Go
- (Package Information): Updated the table to match the new content
standardGo
- (Functional Block Diagram):
Updated/Changed FBD imageGo
- (Functional Block Diagram): Added
software build sheet NoteGo
- (Device Comparison): Added AM68 part numbers to the table. Merged
table cells to show commonality/differences and to improve
readability.Go
- (Device Comparison): Added software build sheet
NoteGo
- (Pin Attributes): Deleted "Buffer Types with Pull Type and Hysteresis Associations"
tableGo
- (Pin Attributes): Added HYS, BUFFER TYPE, and PULL UP/DOWN TYPE
columns to "Pin Attributes (ALZ Package)" tableGo
- (Pin Attributes): Updated/Changed the address range for PADCONFIG_0 through
PADCONFIG_79 registers from "0x4301C000 to 0x4301C11C" to "0x0011C000 to
0x0011C11C"Go
- Dapper test run done 06/22/2023 for J7AEP_dapper_v7Go
- (DDRSS0 Signal Descriptions): Added "DDRSS incremental order" footnoteGo
- (DDRSS1 Signal Descriptions): Added "DDRSS incremental order" footnoteGo
- (MMC0 Signal Descriptions): Deleted the external pull-up connection footnoteGo
- (Pin Connectivity Requirements) Updated ADC AIN recommendation to allow the tie-off
of signals directly to ground.Go
- (Pin Connectivity Requirements): Added requirement for DDR
interfaces to be used in incrementing orderGo
- (Recommended Operating Conditions): Added clarification to the "…
supply inputs" footnote, specifically for VDD_CORE, VDD_MCU, and VDD_CPU domains
plus, added cross-references to the MIN/MAX valuesGo
- (Operating Performance Points): Deleted 'N' speed
grade.Go
- (USB VBUS Design Guidelines): Updated/Changed USB VBUS Detect Voltage Divider
/ Clamp Circuit figureGo