SPRSP92D February   2023  – December 2024 AM69 , AM69A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
      1.      10
      2.      11
    3. 5.3 Signal Descriptions
      1.      13
      2. 5.3.1  ADC
        1. 5.3.1.1 MCU Domain
          1.        16
          2.        17
          3.        18
      3. 5.3.2  DDRSS
        1. 5.3.2.1 MAIN Domain
          1.        21
          2.        22
          3.        23
          4.        24
      4. 5.3.3  GPIO
        1. 5.3.3.1 MAIN Domain
          1.        27
        2. 5.3.3.2 WKUP Domain
          1.        29
      5. 5.3.4  I2C
        1. 5.3.4.1 MAIN Domain
          1.        32
          2.        33
          3.        34
          4.        35
          5.        36
          6.        37
          7.        38
        2. 5.3.4.2 MCU Domain
          1.        40
          2.        41
        3. 5.3.4.3 WKUP Domain
          1.        43
      6. 5.3.5  I3C
        1. 5.3.5.1 MCU Domain
          1.        46
      7. 5.3.6  MCAN
        1. 5.3.6.1 MAIN Domain
          1.        49
          2.        50
          3.        51
          4.        52
          5.        53
          6.        54
          7.        55
          8.        56
          9.        57
          10.        58
          11.        59
          12.        60
          13.        61
          14.        62
          15.        63
          16.        64
          17.        65
          18.        66
        2. 5.3.6.2 MCU Domain
          1.        68
          2.        69
      8. 5.3.7  MCSPI
        1. 5.3.7.1 MAIN Domain
          1.        72
          2.        73
          3.        74
          4.        75
          5.        76
          6.        77
          7.        78
        2. 5.3.7.2 MCU Domain
          1.        80
          2.        81
      9. 5.3.8  UART
        1. 5.3.8.1 MAIN Domain
          1.        84
          2.        85
          3.        86
          4.        87
          5.        88
          6.        89
          7.        90
          8.        91
          9.        92
          10.        93
        2. 5.3.8.2 MCU Domain
          1.        95
        3. 5.3.8.3 WKUP Domain
          1.        97
      10. 5.3.9  MDIO
        1. 5.3.9.1 MAIN Domain
          1.        100
          2.        101
        2. 5.3.9.2 MCU Domain
          1.        103
      11. 5.3.10 UFS
        1. 5.3.10.1 MAIN Domain
          1.        106
      12. 5.3.11 CPSW2G
        1. 5.3.11.1 MAIN Domain
          1.        109
        2. 5.3.11.2 MCU Domain
          1.        111
      13. 5.3.12 SGMII
        1. 5.3.12.1 MAIN Domain
          1.        114
      14. 5.3.13 ECAP
        1. 5.3.13.1 MAIN Domain
          1.        117
          2.        118
          3.        119
      15. 5.3.14 EQEP
        1. 5.3.14.1 MAIN Domain
          1.        122
          2.        123
          3.        124
      16. 5.3.15 EPWM
        1. 5.3.15.1 MAIN Domain
          1.        127
          2.        128
          3.        129
          4.        130
          5.        131
          6.        132
          7.        133
      17. 5.3.16 USB
        1. 5.3.16.1 MAIN Domain
          1.        136
      18. 5.3.17 Display Port
        1. 5.3.17.1 MAIN Domain
          1.        139
      19. 5.3.18 PCIE
        1. 5.3.18.1 MAIN Domain
          1.        142
      20. 5.3.19 SERDES
        1. 5.3.19.1 MAIN Domain
          1.        145
          2.        146
          3.        147
          4.        148
      21. 5.3.20 DSI
        1. 5.3.20.1 MAIN Domain
          1.        151
          2.        152
      22. 5.3.21 CSI
        1. 5.3.21.1 MAIN Domain
          1.        155
          2.        156
          3.        157
      23. 5.3.22 MCASP
        1. 5.3.22.1 MAIN Domain
          1.        160
          2.        161
          3.        162
          4.        163
          5.        164
      24. 5.3.23 DMTIMER
        1. 5.3.23.1 MAIN Domain
          1.        167
        2. 5.3.23.2 MCU Domain
          1.        169
      25. 5.3.24 CPTS
        1. 5.3.24.1 MAIN Domain
          1.        172
        2. 5.3.24.2 MCU Domain
          1.        174
      26. 5.3.25 DSS
        1. 5.3.25.1 MAIN Domain
          1.        177
      27. 5.3.26 GPMC
        1. 5.3.26.1 MAIN Domain
          1.        180
      28. 5.3.27 MMC
        1. 5.3.27.1 MAIN Domain
          1.        183
          2.        184
      29. 5.3.28 OSPI
        1. 5.3.28.1 MCU Domain
          1.        187
          2.        188
      30. 5.3.29 Hyperbus
        1. 5.3.29.1 MCU Domain
          1.        191
      31. 5.3.30 Emulation and Debug
        1. 5.3.30.1 MAIN Domain
          1.        194
          2.        195
      32. 5.3.31 System and Miscellaneous
        1. 5.3.31.1 Boot Mode configuration
          1.        198
        2. 5.3.31.2 Clock
          1.        200
          2.        201
        3. 5.3.31.3 System
          1.        203
          2.        204
        4. 5.3.31.4 EFUSE
          1.        206
        5. 5.3.31.5 VMON
          1.        208
      33. 5.3.32 Power
        1.       210
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On-Hour (POH) Limits
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Operating Performance Points
    6. 6.6  Electrical Characteristics
      1. 6.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 6.6.3  HFOSC/LFOSC Electrical Characteristics
      4. 6.6.4  eMMCPHY Electrical Characteristics
      5. 6.6.5  SDIO Electrical Characteristics
      6. 6.6.6  CSI2/DSI D-PHY Electrical Characteristics
      7. 6.6.7  ADC12B Electrical Characteristics
      8. 6.6.8  LVCMOS Electrical Characteristics
      9. 6.6.9  USB2PHY Electrical Characteristics
      10. 6.6.10 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics
      11. 6.6.11 UFS M-PHY Electrical Characteristics
      12. 6.6.12 eDP/DP AUX-PHY Electrical Characteristics
      13. 6.6.13 DDR0 Electrical Characteristics
    7. 6.7  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.7.2 Hardware Requirements
      3. 6.7.3 Programming Sequence
      4. 6.7.4 Impact to Your Hardware Warranty
    8. 6.8  Thermal Resistance Characteristics
      1. 6.8.1 Thermal Resistance Characteristics for ALY Package
      2. 6.8.2 Thermal Resistance Characteristics for AND Package
    9. 6.9  Temperature Sensor Characteristics
    10. 6.10 Timing and Switching Characteristics
      1. 6.10.1 Timing Parameters and Information
      2. 6.10.2 Power Supply Sequencing
        1. 6.10.2.1 Power Supply Slew Rate Requirement
        2. 6.10.2.2 Combined MCU and Main Domains Power- Up Sequencing
        3. 6.10.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 6.10.2.4 Isolated MCU and Main Domains Power- Up Sequencing
        5. 6.10.2.5 Isolated MCU and Main Domains Power- Down Sequencing
        6. 6.10.2.6 Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
        7. 6.10.2.7 Independent MCU and Main Domains, Entry and Exit of DDR Retention State
        8. 6.10.2.8 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
      3. 6.10.3 System Timing
        1. 6.10.3.1 Reset Timing
        2. 6.10.3.2 Safety Signal Timing
        3. 6.10.3.3 Clock Timing
      4. 6.10.4 Clock Specifications
        1. 6.10.4.1 Input and Output Clocks / Oscillators
          1. 6.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 6.10.4.1.1.1 Load Capacitance
            2. 6.10.4.1.1.2 Shunt Capacitance
          2. 6.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 6.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 6.10.4.1.3.1 Load Capacitance
            2. 6.10.4.1.3.2 Shunt Capacitance
          4. 6.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 6.10.4.1.5 Auxiliary OSC1 Not Used
        2. 6.10.4.2 Output Clocks
        3. 6.10.4.3 PLLs
        4. 6.10.4.4 Module and Peripheral Clocks Frequencies
      5. 6.10.5 Peripherals
        1. 6.10.5.1  ATL
          1. 6.10.5.1.1 ATL_PCLK Timing Requirements
          2. 6.10.5.1.2 ATL_AWS[x] Timing Requirements
          3. 6.10.5.1.3 ATL_BWS[x] Timing Requirements
          4. 6.10.5.1.4 ATCLK[x] Switching Characteristics
        2. 6.10.5.2  CPSW2G
          1. 6.10.5.2.1 CPSW2G MDIO Interface Timings
          2. 6.10.5.2.2 CPSW2G RMII Timings
            1. 6.10.5.2.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 6.10.5.2.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 6.10.5.2.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 6.10.5.2.3 CPSW2G RGMII Timings
            1. 6.10.5.2.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 6.10.5.2.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 6.10.5.2.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 6.10.5.2.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        3. 6.10.5.3  CSI-2
        4. 6.10.5.4  DDRSS
        5. 6.10.5.5  DSS
        6. 6.10.5.6  eCAP
          1. 6.10.5.6.1 Timing Requirements for eCAP
          2. 6.10.5.6.2 Switching Characteristics for eCAP
        7. 6.10.5.7  EPWM
          1. 6.10.5.7.1 Timing Requirements for eHRPWM
          2. 6.10.5.7.2 Switching Characteristics for eHRPWM
        8. 6.10.5.8  eQEP
          1. 6.10.5.8.1 Timing Requirements for eQEP
          2. 6.10.5.8.2 Switching Characteristics for eQEP
        9. 6.10.5.9  GPIO
          1. 6.10.5.9.1 GPIO Timing Requirements
          2. 6.10.5.9.2 GPIO Switching Characteristics
        10. 6.10.5.10 GPMC
          1. 6.10.5.10.1 GPMC and NOR Flash — Synchronous Mode
            1. 6.10.5.10.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 6.10.5.10.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 6.10.5.10.2 GPMC and NOR Flash — Asynchronous Mode
            1. 6.10.5.10.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 6.10.5.10.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 6.10.5.10.3 GPMC and NAND Flash — Asynchronous Mode
            1. 6.10.5.10.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 6.10.5.10.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
          4. 6.10.5.10.4 GPMC0 IOSET
        11. 6.10.5.11 HyperBus
          1. 6.10.5.11.1 Timing Requirements for HyperBus
          2. 6.10.5.11.2 HyperBus 166 MHz Switching Characteristics
          3. 6.10.5.11.3 HyperBus 100 MHz Switching Characteristics
        12. 6.10.5.12 I2C
        13. 6.10.5.13 I3C
        14. 6.10.5.14 MCAN
        15. 6.10.5.15 MCASP
        16. 6.10.5.16 MCSPI
          1. 6.10.5.16.1 MCSPI — Controller Mode
          2. 6.10.5.16.2 MCSPI — Peripheral Mode
        17. 6.10.5.17 MMCSD
          1. 6.10.5.17.1 MMC0 - eMMC Interface
            1. 6.10.5.17.1.1 Legacy SDR Mode
            2. 6.10.5.17.1.2 High Speed SDR Mode
            3. 6.10.5.17.1.3 High Speed DDR Mode
            4. 6.10.5.17.1.4 HS200 Mode
            5. 6.10.5.17.1.5 HS400 Mode
          2. 6.10.5.17.2 MMC1/2 - SD/SDIO Interface
            1. 6.10.5.17.2.1 Default Speed Mode
            2. 6.10.5.17.2.2 High Speed Mode
            3. 6.10.5.17.2.3 UHS–I SDR12 Mode
            4. 6.10.5.17.2.4 UHS–I SDR25 Mode
            5. 6.10.5.17.2.5 UHS–I SDR50 Mode
            6. 6.10.5.17.2.6 UHS–I DDR50 Mode
            7. 6.10.5.17.2.7 UHS–I SDR104 Mode
        18. 6.10.5.18 CPTS
          1. 6.10.5.18.1 CPTS Timing Requirements
          2. 6.10.5.18.2 CPTS Switching Characteristics
        19. 6.10.5.19 OSPI
          1. 6.10.5.19.1 OSPI0/1 PHY Mode
            1. 6.10.5.19.1.1 OSPI0/1 With PHY Data Training
            2. 6.10.5.19.1.2 OSPI Without Data Training
              1. 6.10.5.19.1.2.1 OSPI Timing Requirements – SDR Mode
              2. 6.10.5.19.1.2.2 OSPI Switching Characteristics – SDR Mode
              3. 6.10.5.19.1.2.3 OSPI Timing Requirements – DDR Mode
              4. 6.10.5.19.1.2.4 OSPI Switching Characteristics – PHY DDR Mode
          2. 6.10.5.19.2 OSPI0/1 Tap Mode
            1. 6.10.5.19.2.1 OSPI0 Tap SDR Timing
            2. 6.10.5.19.2.2 OSPI0 Tap DDR Timing
        20. 6.10.5.20 OLDI
          1. 6.10.5.20.1 OLDI Switching Characteristics
        21. 6.10.5.21 PCIE
        22. 6.10.5.22 Timers
          1. 6.10.5.22.1 Timing Requirements for Timers
          2. 6.10.5.22.2 Switching Characteristics for Timers
        23. 6.10.5.23 UART
          1. 6.10.5.23.1 Timing Requirements for UART
          2. 6.10.5.23.2 UART Switching Characteristics
        24. 6.10.5.24 USB
      6. 6.10.6 Emulation and Debug
        1. 6.10.6.1 Trace
        2. 6.10.6.2 JTAG
          1. 6.10.6.2.1 JTAG Electrical Data and Timing
            1. 6.10.6.2.1.1 JTAG Timing Requirements
            2. 6.10.6.2.1.2 JTAG Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Processor Subsystems
      1. 7.3.1 Arm Cortex-A72
      2. 7.3.2 Arm Cortex-R5F
      3. 7.3.3 DSP C71x
    4. 7.4 Accelerators and Coprocessors
      1. 7.4.1 GPU
      2. 7.4.2 VPAC
      3. 7.4.3 DMPAC
    5. 7.5 Other Subsystems
      1. 7.5.1 MSMC
      2. 7.5.2 NAVSS
        1. 7.5.2.1 NAVSS0
        2. 7.5.2.2 MCU_NAVSS
      3. 7.5.3 PDMA Controller
      4. 7.5.4 Power Supply
      5. 7.5.5 Peripherals
        1. 7.5.5.1  ADC
        2. 7.5.5.2  ATL
        3. 7.5.5.3  CSI
          1. 7.5.5.3.1 Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)
          2. 7.5.5.3.2 Camera Streaming Interface Transmitter (CSI_TX_IF)
        4. 7.5.5.4  CPSW2G
        5. 7.5.5.5  CPSW9G
        6. 7.5.5.6  DCC
        7. 7.5.5.7  DDRSS
        8. 7.5.5.8  DSS
          1. 7.5.5.8.1 DSI
          2. 7.5.5.8.2 eDP
        9. 7.5.5.9  eCAP
        10. 7.5.5.10 EPWM
        11. 7.5.5.11 ELM
        12. 7.5.5.12 ESM
        13. 7.5.5.13 eQEP
        14. 7.5.5.14 GPIO
        15. 7.5.5.15 GPMC
        16. 7.5.5.16 Hyperbus
        17. 7.5.5.17 I2C
        18. 7.5.5.18 I3C
        19. 7.5.5.19 MCAN
        20. 7.5.5.20 MCASP
        21. 7.5.5.21 MCRC Controller
        22. 7.5.5.22 MCSPI
        23. 7.5.5.23 MMC/SD
        24. 7.5.5.24 OSPI
        25. 7.5.5.25 PCIE
        26. 7.5.5.26 SerDes
        27. 7.5.5.27 WWDT
        28. 7.5.5.28 Timers
        29. 7.5.5.29 UART
        30. 7.5.5.30 USB
        31. 7.5.5.31 UFS
  9. 8 Applications, Implementation, and Layout
  10. 9 Device Connection and Layout Fundamentals
    1. 9.1 Power Supply Decoupling and Bulk Capacitors
      1. 9.1.1 Power Distribution Network Implementation Guidance
    2. 9.2 External Oscillator
    3. 9.3 JTAG and EMU
    4. 9.4 Reset
    5. 9.5 Unused Pins
    6. 9.6 Hardware Design Guide for JacintoTM 7 Devices
  11. 10Peripheral- and Interface-Specific Design Information
    1. 10.1 LPDDR4 Board Design and Layout Guidelines
    2. 10.2 OSPI and QSPI Board Design and Layout Guidelines
      1. 10.2.1 No Loopback and Internal Pad Loopback
      2. 10.2.2 External Board Loopback
      3. 10.2.3 DQS (only available in Octal Flash devices)
    3. 10.3 USB VBUS Design Guidelines
    4. 10.4 System Power Supply Monitor Design Guidelines using VMON/POK
    5. 10.5 High Speed Differential Signal Routing Guidance
    6. 10.6 Thermal Solution Guidance
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
      1. 11.1.1 Standard Package Symbolization
      2. 11.1.2 Device Naming Convention
    2. 11.2 Tools and Software
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALY|1414
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 5-7 DDRSS2 Signal Descriptions
SIGNAL NAME [1] ((4)) ((3))PIN TYPE [2]DESCRIPTION [3]ALY PIN [4]AND PIN [4]
DDR2_CKN (1)IODDRSS Differential Clock (negative)K1
DDR2_CKP (1)IODDRSS Differential Clock (positive)L2
DDR2_RESETn (1)IODDRSS Reset J5
DDR2_RET (1)IDDR Retention EnableL8
DDR2_CA0 (1)IODDRS Command AddressK3
DDR2_CA1 (1)IODDRS Command AddressL3
DDR2_CA2 (1)IODDRS Command AddressK5
DDR2_CA3 (1)IODDRS Command AddressL4
DDR2_CA4 (1)IODDRS Command AddressK4
DDR2_CA5 (1)IODDRS Command AddressL7
DDR2_CAL0 (1) (2)ADDRSS IO Pad Calibration ResistorU7
DDR2_CKE0 (1)IODDR Clock EnableL6
DDR2_CKE1 (1)IODDR Clock EnableJ2
DDR2_CSn0_0 (1)IODDRSS Chip SelectJ3
DDR2_CSn0_1 (1)IODDRSS Chip SelectJ6
DDR2_CSn1_0 (1)IODDRSS Chip SelectJ7
DDR2_CSn1_1 (1)IODDRSS Chip SelectK7
DDR2_DM0 (1)IODDRSS Data MaskT2
DDR2_DM1 (1)IODDRSS Data MaskM6
DDR2_DM2 (1)IODDRSS Data MaskG4
DDR2_DM3 (1)IODDRSS Data MaskD5
DDR2_DQ0 (1)IODDRSS DataT4
DDR2_DQ1 (1)IODDRSS DataR6
DDR2_DQ2 (1)IODDRSS DataR3
DDR2_DQ3 (1)IODDRSS DataR4
DDR2_DQ4 (1)IODDRSS DataP6
DDR2_DQ5 (1)IODDRSS DataP5
DDR2_DQ6 (1)IODDRSS DataT5
DDR2_DQ7 (1)IODDRSS DataR7
DDR2_DQ8 (1)IODDRSS DataN2
DDR2_DQ9 (1)IODDRSS DataN4
DDR2_DQ10 (1)IODDRSS DataP2
DDR2_DQ11 (1)IODDRSS DataP3
DDR2_DQ12 (1)IODDRSS DataM7
DDR2_DQ13 (1)IODDRSS DataN5
DDR2_DQ14 (1)IODDRSS DataM4
DDR2_DQ15 (1)IODDRSS DataM3
DDR2_DQ16 (1)IODDRSS DataF3
DDR2_DQ17 (1)IODDRSS DataG7
DDR2_DQ18 (1)IODDRSS DataH6
DDR2_DQ19 (1)IODDRSS DataH4
DDR2_DQ20 (1)IODDRSS DataG2
DDR2_DQ21 (1)IODDRSS DataH3
DDR2_DQ22 (1)IODDRSS DataG5
DDR2_DQ23 (1)IODDRSS DataF2
DDR2_DQ24 (1)IODDRSS DataE4
DDR2_DQ25 (1)IODDRSS DataD2
DDR2_DQ26 (1)IODDRSS DataF6
DDR2_DQ27 (1)IODDRSS DataF5
DDR2_DQ28 (1)IODDRSS DataE3
DDR2_DQ29 (1)IODDRSS DataE7
DDR2_DQ30 (1)IODDRSS DataE6
DDR2_DQ31 (1)IODDRSS DataD4
DDR2_DQS0N (1)IODDRS Complimentary Data StrobeR1
DDR2_DQS0P (1)IODDRS Data StrobeT1
DDR2_DQS1N (1)IODDRS Complimentary Data StrobeM1
DDR2_DQS1P (1)IODDRS Data StrobeN1
DDR2_DQS2N (1)IODDRS Complimentary Data StrobeG1
DDR2_DQS2P (1)IODDRS Data StrobeH1
DDR2_DQS3N (1)IODDRS Complimentary Data StrobeD1
DDR2_DQS3P (1)IODDRS Data StrobeE1
(1) This signal is not supported on AM69A94, AM6954 devices. Please refer to Device Comparison and Pin Attributes table for the complete list of supported IP and signals.
(2) An external 240 Ω ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.
(3) DDRSS0, DDRSS1, DDRSS2, and DDRSS3 must always be used in incremental order. For instance, when using a single LPDDR component, it must be connected to the DDR0_* interface. When using two LPDDR components, they must be connected to DDR0_* and DDR1_* interfaces, and so forth.
(4) DDRSS2, DDRSS3, and SERDES2 are not available on the 27mm package variant of this SoC. DDRSS2/DDRSS3/SERDES2 should be avoided if software compatibility is desired with systems that use the 27mm package.