SPRSP92D February   2023  – December 2024 AM69 , AM69A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
      1.      10
      2.      11
    3. 5.3 Signal Descriptions
      1.      13
      2. 5.3.1  ADC
        1. 5.3.1.1 MCU Domain
          1.        16
          2.        17
          3.        18
      3. 5.3.2  DDRSS
        1. 5.3.2.1 MAIN Domain
          1.        21
          2.        22
          3.        23
          4.        24
      4. 5.3.3  GPIO
        1. 5.3.3.1 MAIN Domain
          1.        27
        2. 5.3.3.2 WKUP Domain
          1.        29
      5. 5.3.4  I2C
        1. 5.3.4.1 MAIN Domain
          1.        32
          2.        33
          3.        34
          4.        35
          5.        36
          6.        37
          7.        38
        2. 5.3.4.2 MCU Domain
          1.        40
          2.        41
        3. 5.3.4.3 WKUP Domain
          1.        43
      6. 5.3.5  I3C
        1. 5.3.5.1 MCU Domain
          1.        46
      7. 5.3.6  MCAN
        1. 5.3.6.1 MAIN Domain
          1.        49
          2.        50
          3.        51
          4.        52
          5.        53
          6.        54
          7.        55
          8.        56
          9.        57
          10.        58
          11.        59
          12.        60
          13.        61
          14.        62
          15.        63
          16.        64
          17.        65
          18.        66
        2. 5.3.6.2 MCU Domain
          1.        68
          2.        69
      8. 5.3.7  MCSPI
        1. 5.3.7.1 MAIN Domain
          1.        72
          2.        73
          3.        74
          4.        75
          5.        76
          6.        77
          7.        78
        2. 5.3.7.2 MCU Domain
          1.        80
          2.        81
      9. 5.3.8  UART
        1. 5.3.8.1 MAIN Domain
          1.        84
          2.        85
          3.        86
          4.        87
          5.        88
          6.        89
          7.        90
          8.        91
          9.        92
          10.        93
        2. 5.3.8.2 MCU Domain
          1.        95
        3. 5.3.8.3 WKUP Domain
          1.        97
      10. 5.3.9  MDIO
        1. 5.3.9.1 MAIN Domain
          1.        100
          2.        101
        2. 5.3.9.2 MCU Domain
          1.        103
      11. 5.3.10 UFS
        1. 5.3.10.1 MAIN Domain
          1.        106
      12. 5.3.11 CPSW2G
        1. 5.3.11.1 MAIN Domain
          1.        109
        2. 5.3.11.2 MCU Domain
          1.        111
      13. 5.3.12 SGMII
        1. 5.3.12.1 MAIN Domain
          1.        114
      14. 5.3.13 ECAP
        1. 5.3.13.1 MAIN Domain
          1.        117
          2.        118
          3.        119
      15. 5.3.14 EQEP
        1. 5.3.14.1 MAIN Domain
          1.        122
          2.        123
          3.        124
      16. 5.3.15 EPWM
        1. 5.3.15.1 MAIN Domain
          1.        127
          2.        128
          3.        129
          4.        130
          5.        131
          6.        132
          7.        133
      17. 5.3.16 USB
        1. 5.3.16.1 MAIN Domain
          1.        136
      18. 5.3.17 Display Port
        1. 5.3.17.1 MAIN Domain
          1.        139
      19. 5.3.18 PCIE
        1. 5.3.18.1 MAIN Domain
          1.        142
      20. 5.3.19 SERDES
        1. 5.3.19.1 MAIN Domain
          1.        145
          2.        146
          3.        147
          4.        148
      21. 5.3.20 DSI
        1. 5.3.20.1 MAIN Domain
          1.        151
          2.        152
      22. 5.3.21 CSI
        1. 5.3.21.1 MAIN Domain
          1.        155
          2.        156
          3.        157
      23. 5.3.22 MCASP
        1. 5.3.22.1 MAIN Domain
          1.        160
          2.        161
          3.        162
          4.        163
          5.        164
      24. 5.3.23 DMTIMER
        1. 5.3.23.1 MAIN Domain
          1.        167
        2. 5.3.23.2 MCU Domain
          1.        169
      25. 5.3.24 CPTS
        1. 5.3.24.1 MAIN Domain
          1.        172
        2. 5.3.24.2 MCU Domain
          1.        174
      26. 5.3.25 DSS
        1. 5.3.25.1 MAIN Domain
          1.        177
      27. 5.3.26 GPMC
        1. 5.3.26.1 MAIN Domain
          1.        180
      28. 5.3.27 MMC
        1. 5.3.27.1 MAIN Domain
          1.        183
          2.        184
      29. 5.3.28 OSPI
        1. 5.3.28.1 MCU Domain
          1.        187
          2.        188
      30. 5.3.29 Hyperbus
        1. 5.3.29.1 MCU Domain
          1.        191
      31. 5.3.30 Emulation and Debug
        1. 5.3.30.1 MAIN Domain
          1.        194
          2.        195
      32. 5.3.31 System and Miscellaneous
        1. 5.3.31.1 Boot Mode configuration
          1.        198
        2. 5.3.31.2 Clock
          1.        200
          2.        201
        3. 5.3.31.3 System
          1.        203
          2.        204
        4. 5.3.31.4 EFUSE
          1.        206
        5. 5.3.31.5 VMON
          1.        208
      33. 5.3.32 Power
        1.       210
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On-Hour (POH) Limits
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Operating Performance Points
    6. 6.6  Electrical Characteristics
      1. 6.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 6.6.3  HFOSC/LFOSC Electrical Characteristics
      4. 6.6.4  eMMCPHY Electrical Characteristics
      5. 6.6.5  SDIO Electrical Characteristics
      6. 6.6.6  CSI2/DSI D-PHY Electrical Characteristics
      7. 6.6.7  ADC12B Electrical Characteristics
      8. 6.6.8  LVCMOS Electrical Characteristics
      9. 6.6.9  USB2PHY Electrical Characteristics
      10. 6.6.10 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics
      11. 6.6.11 UFS M-PHY Electrical Characteristics
      12. 6.6.12 eDP/DP AUX-PHY Electrical Characteristics
      13. 6.6.13 DDR0 Electrical Characteristics
    7. 6.7  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.7.2 Hardware Requirements
      3. 6.7.3 Programming Sequence
      4. 6.7.4 Impact to Your Hardware Warranty
    8. 6.8  Thermal Resistance Characteristics
      1. 6.8.1 Thermal Resistance Characteristics for ALY Package
      2. 6.8.2 Thermal Resistance Characteristics for AND Package
    9. 6.9  Temperature Sensor Characteristics
    10. 6.10 Timing and Switching Characteristics
      1. 6.10.1 Timing Parameters and Information
      2. 6.10.2 Power Supply Sequencing
        1. 6.10.2.1 Power Supply Slew Rate Requirement
        2. 6.10.2.2 Combined MCU and Main Domains Power- Up Sequencing
        3. 6.10.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 6.10.2.4 Isolated MCU and Main Domains Power- Up Sequencing
        5. 6.10.2.5 Isolated MCU and Main Domains Power- Down Sequencing
        6. 6.10.2.6 Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
        7. 6.10.2.7 Independent MCU and Main Domains, Entry and Exit of DDR Retention State
        8. 6.10.2.8 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
      3. 6.10.3 System Timing
        1. 6.10.3.1 Reset Timing
        2. 6.10.3.2 Safety Signal Timing
        3. 6.10.3.3 Clock Timing
      4. 6.10.4 Clock Specifications
        1. 6.10.4.1 Input and Output Clocks / Oscillators
          1. 6.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 6.10.4.1.1.1 Load Capacitance
            2. 6.10.4.1.1.2 Shunt Capacitance
          2. 6.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 6.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 6.10.4.1.3.1 Load Capacitance
            2. 6.10.4.1.3.2 Shunt Capacitance
          4. 6.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 6.10.4.1.5 Auxiliary OSC1 Not Used
        2. 6.10.4.2 Output Clocks
        3. 6.10.4.3 PLLs
        4. 6.10.4.4 Module and Peripheral Clocks Frequencies
      5. 6.10.5 Peripherals
        1. 6.10.5.1  ATL
          1. 6.10.5.1.1 ATL_PCLK Timing Requirements
          2. 6.10.5.1.2 ATL_AWS[x] Timing Requirements
          3. 6.10.5.1.3 ATL_BWS[x] Timing Requirements
          4. 6.10.5.1.4 ATCLK[x] Switching Characteristics
        2. 6.10.5.2  CPSW2G
          1. 6.10.5.2.1 CPSW2G MDIO Interface Timings
          2. 6.10.5.2.2 CPSW2G RMII Timings
            1. 6.10.5.2.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 6.10.5.2.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 6.10.5.2.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 6.10.5.2.3 CPSW2G RGMII Timings
            1. 6.10.5.2.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 6.10.5.2.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 6.10.5.2.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 6.10.5.2.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        3. 6.10.5.3  CSI-2
        4. 6.10.5.4  DDRSS
        5. 6.10.5.5  DSS
        6. 6.10.5.6  eCAP
          1. 6.10.5.6.1 Timing Requirements for eCAP
          2. 6.10.5.6.2 Switching Characteristics for eCAP
        7. 6.10.5.7  EPWM
          1. 6.10.5.7.1 Timing Requirements for eHRPWM
          2. 6.10.5.7.2 Switching Characteristics for eHRPWM
        8. 6.10.5.8  eQEP
          1. 6.10.5.8.1 Timing Requirements for eQEP
          2. 6.10.5.8.2 Switching Characteristics for eQEP
        9. 6.10.5.9  GPIO
          1. 6.10.5.9.1 GPIO Timing Requirements
          2. 6.10.5.9.2 GPIO Switching Characteristics
        10. 6.10.5.10 GPMC
          1. 6.10.5.10.1 GPMC and NOR Flash — Synchronous Mode
            1. 6.10.5.10.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 6.10.5.10.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 6.10.5.10.2 GPMC and NOR Flash — Asynchronous Mode
            1. 6.10.5.10.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 6.10.5.10.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 6.10.5.10.3 GPMC and NAND Flash — Asynchronous Mode
            1. 6.10.5.10.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 6.10.5.10.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
          4. 6.10.5.10.4 GPMC0 IOSET
        11. 6.10.5.11 HyperBus
          1. 6.10.5.11.1 Timing Requirements for HyperBus
          2. 6.10.5.11.2 HyperBus 166 MHz Switching Characteristics
          3. 6.10.5.11.3 HyperBus 100 MHz Switching Characteristics
        12. 6.10.5.12 I2C
        13. 6.10.5.13 I3C
        14. 6.10.5.14 MCAN
        15. 6.10.5.15 MCASP
        16. 6.10.5.16 MCSPI
          1. 6.10.5.16.1 MCSPI — Controller Mode
          2. 6.10.5.16.2 MCSPI — Peripheral Mode
        17. 6.10.5.17 MMCSD
          1. 6.10.5.17.1 MMC0 - eMMC Interface
            1. 6.10.5.17.1.1 Legacy SDR Mode
            2. 6.10.5.17.1.2 High Speed SDR Mode
            3. 6.10.5.17.1.3 High Speed DDR Mode
            4. 6.10.5.17.1.4 HS200 Mode
            5. 6.10.5.17.1.5 HS400 Mode
          2. 6.10.5.17.2 MMC1/2 - SD/SDIO Interface
            1. 6.10.5.17.2.1 Default Speed Mode
            2. 6.10.5.17.2.2 High Speed Mode
            3. 6.10.5.17.2.3 UHS–I SDR12 Mode
            4. 6.10.5.17.2.4 UHS–I SDR25 Mode
            5. 6.10.5.17.2.5 UHS–I SDR50 Mode
            6. 6.10.5.17.2.6 UHS–I DDR50 Mode
            7. 6.10.5.17.2.7 UHS–I SDR104 Mode
        18. 6.10.5.18 CPTS
          1. 6.10.5.18.1 CPTS Timing Requirements
          2. 6.10.5.18.2 CPTS Switching Characteristics
        19. 6.10.5.19 OSPI
          1. 6.10.5.19.1 OSPI0/1 PHY Mode
            1. 6.10.5.19.1.1 OSPI0/1 With PHY Data Training
            2. 6.10.5.19.1.2 OSPI Without Data Training
              1. 6.10.5.19.1.2.1 OSPI Timing Requirements – SDR Mode
              2. 6.10.5.19.1.2.2 OSPI Switching Characteristics – SDR Mode
              3. 6.10.5.19.1.2.3 OSPI Timing Requirements – DDR Mode
              4. 6.10.5.19.1.2.4 OSPI Switching Characteristics – PHY DDR Mode
          2. 6.10.5.19.2 OSPI0/1 Tap Mode
            1. 6.10.5.19.2.1 OSPI0 Tap SDR Timing
            2. 6.10.5.19.2.2 OSPI0 Tap DDR Timing
        20. 6.10.5.20 OLDI
          1. 6.10.5.20.1 OLDI Switching Characteristics
        21. 6.10.5.21 PCIE
        22. 6.10.5.22 Timers
          1. 6.10.5.22.1 Timing Requirements for Timers
          2. 6.10.5.22.2 Switching Characteristics for Timers
        23. 6.10.5.23 UART
          1. 6.10.5.23.1 Timing Requirements for UART
          2. 6.10.5.23.2 UART Switching Characteristics
        24. 6.10.5.24 USB
      6. 6.10.6 Emulation and Debug
        1. 6.10.6.1 Trace
        2. 6.10.6.2 JTAG
          1. 6.10.6.2.1 JTAG Electrical Data and Timing
            1. 6.10.6.2.1.1 JTAG Timing Requirements
            2. 6.10.6.2.1.2 JTAG Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Processor Subsystems
      1. 7.3.1 Arm Cortex-A72
      2. 7.3.2 Arm Cortex-R5F
      3. 7.3.3 DSP C71x
    4. 7.4 Accelerators and Coprocessors
      1. 7.4.1 GPU
      2. 7.4.2 VPAC
      3. 7.4.3 DMPAC
    5. 7.5 Other Subsystems
      1. 7.5.1 MSMC
      2. 7.5.2 NAVSS
        1. 7.5.2.1 NAVSS0
        2. 7.5.2.2 MCU_NAVSS
      3. 7.5.3 PDMA Controller
      4. 7.5.4 Power Supply
      5. 7.5.5 Peripherals
        1. 7.5.5.1  ADC
        2. 7.5.5.2  ATL
        3. 7.5.5.3  CSI
          1. 7.5.5.3.1 Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)
          2. 7.5.5.3.2 Camera Streaming Interface Transmitter (CSI_TX_IF)
        4. 7.5.5.4  CPSW2G
        5. 7.5.5.5  CPSW9G
        6. 7.5.5.6  DCC
        7. 7.5.5.7  DDRSS
        8. 7.5.5.8  DSS
          1. 7.5.5.8.1 DSI
          2. 7.5.5.8.2 eDP
        9. 7.5.5.9  eCAP
        10. 7.5.5.10 EPWM
        11. 7.5.5.11 ELM
        12. 7.5.5.12 ESM
        13. 7.5.5.13 eQEP
        14. 7.5.5.14 GPIO
        15. 7.5.5.15 GPMC
        16. 7.5.5.16 Hyperbus
        17. 7.5.5.17 I2C
        18. 7.5.5.18 I3C
        19. 7.5.5.19 MCAN
        20. 7.5.5.20 MCASP
        21. 7.5.5.21 MCRC Controller
        22. 7.5.5.22 MCSPI
        23. 7.5.5.23 MMC/SD
        24. 7.5.5.24 OSPI
        25. 7.5.5.25 PCIE
        26. 7.5.5.26 SerDes
        27. 7.5.5.27 WWDT
        28. 7.5.5.28 Timers
        29. 7.5.5.29 UART
        30. 7.5.5.30 USB
        31. 7.5.5.31 UFS
  9. 8 Applications, Implementation, and Layout
  10. 9 Device Connection and Layout Fundamentals
    1. 9.1 Power Supply Decoupling and Bulk Capacitors
      1. 9.1.1 Power Distribution Network Implementation Guidance
    2. 9.2 External Oscillator
    3. 9.3 JTAG and EMU
    4. 9.4 Reset
    5. 9.5 Unused Pins
    6. 9.6 Hardware Design Guide for JacintoTM 7 Devices
  11. 10Peripheral- and Interface-Specific Design Information
    1. 10.1 LPDDR4 Board Design and Layout Guidelines
    2. 10.2 OSPI and QSPI Board Design and Layout Guidelines
      1. 10.2.1 No Loopback and Internal Pad Loopback
      2. 10.2.2 External Board Loopback
      3. 10.2.3 DQS (only available in Octal Flash devices)
    3. 10.3 USB VBUS Design Guidelines
    4. 10.4 System Power Supply Monitor Design Guidelines using VMON/POK
    5. 10.5 High Speed Differential Signal Routing Guidance
    6. 10.6 Thermal Solution Guidance
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
      1. 11.1.1 Standard Package Symbolization
      2. 11.1.2 Device Naming Convention
    2. 11.2 Tools and Software
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALY|1414
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.10.5.10.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode

NO.(2)PARAMETERDESCRIPTIONMODE(19)MINMAXMINMAXUNIT
100 MHz(20)133 MHz(20)
F0tc(clk)Period, output clock GPMC_CLK(18)div_by_1_mode;
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		107.52ns
F1tw(clkH)Typical pulse duration, output clock GPMC_CLK highdiv_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 0.475*P(15)- 0.3 0.475*P(15)- 0.3ns
F1tw(clkL)Typical pulse duration, output clock GPMC_CLK lowdiv_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		 0.475*P(15)- 0.3 0.475*P(15)- 0.3ns
F2td(clkH-csnV)Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[i] transition(14)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
no extra_delay		F(6)- 2.2F+3.75F(6)- 2.2F(6)+ 3.75ns
F3td(clkH-CSn[i]V)Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[i] invalid(14)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
no extra_delay		E(5)- 2.2E(5)+ 3.75E(5)- 2.2E(5)+ 3.75ns
F4td(aV-clk)Delay time, output address GPMC_A[27:1] valid to output clock GPMC_CLK first edgediv_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		B(2)-2.3B(2)+4.5B(2)-2.3B(2)+4.5ns
F5td(clkH-aIV)Delay time, output clock GPMC_CLK rising edge to output address GPMC_A[27:1] invaliddiv_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		–2.34.5–2.34.5ns
F6td(be[x]nV-clk)Delay time, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n valid to output clock GPMC_CLK first edgediv_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		B(2)-2.3B(2)+1.9B(2)-2.3B(2)+1.9ns
F7td(clkH-be[x]nIV)Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n invalid(11)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		D(4)-2.3D(4)+1.9D(4)-2.3D(4)+1.9ns
F7td(clkL-be[x]nIV)Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid(12)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		D(4)-2.3D(4)+1.9D(4)-2.3D(4)+1.9ns
F7td(clkL-be[x]nIV).Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid(13)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		D(4)-2.3D(4)+1.9D(4)-2.3D(4)+1.9ns
F8td(clkH-advn)Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE transitiondiv_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
no extra_delay		G(7)-2.3G(7)+4.5G(7)-2.3G(7)+4.5ns
F9td(clkH-advnIV)Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE invaliddiv_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
no extra_delay		D(4)-2.3D(4)+4.5D(4)-2.3D(4)+4.5ns
F10td(clkH-oen)Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn transitiondiv_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
no extra_delay		H(8)-2.3H(8)+3.5H(8)-2.3H(8)+3.5ns
F11td(clkH-oenIV)Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn invaliddiv_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
no extra_delay		E(8)-2.3E(8)+3.5E(8)-2.3E(8)+ 3.5ns
F14td(clkH-wen)Delay time, output clock GPMC_CLK rising edge to output write enable GPMC_WEn transitiondiv_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
no extra_delay		I(9)- 2.3I(9)+4.5I(9)- 2.3I(9)+4.5ns
F15td(clkH-do)Delay time, output clock GPMC_CLK rising edge to output data GPMC_AD[15:0] transition(11)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		J(10)-2.3J(10)+2.7J(10)-2.3J(10)+2.7ns
F15td(clkL-do)Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition(12)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		J(10)-2.3J(10)+2.7J(10)-2.3J(10)+2.7ns
F15td(clkL-do).Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition(13)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		J(10)-2.3J(10)+2.7J(10)-2.3J(10)+2.7ns
F17td(clkH-be[x]n)Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE transition(11)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		J(10)-2.3J(10)+1.9J(10)-2.3J(10)+1.9ns
F17td(clkL-be[x]n)Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition(12)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		J(10)-2.3J(10)+1.9J(10)-2.3J(10)+1.9ns
F17td(clkL-be[x]n).Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition(13)div_by_1_mode
; GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1		J(10)-2.3J(10)+1.9J(10)-2.3J(10)+1.9ns
F18tw(csnV)Pulse duration, output chip select GPMC_CSn[i] low(14)ReadA(1)A(1)ns
WriteA(1)A(1)ns
F19tw(be[x]nV)Pulse duration, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n lowReadC(3)C(3)ns
WriteC(3)C(3)ns
F20tw(advnV)Pulse duration, output address valid and address latch enable GPMC_ADVn_ALE lowReadK(16)K(16)ns
WriteK(16)K(16)ns
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
With n being the page burst access number.
(2) B = ClkActivationTime × GPMC_FCLK(17)
(3) For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: C = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: C = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
With n being the page burst access number.
(4) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
(5) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
(6) For csn falling edge (CS activated):
  • Case GPMCFCLKDIVIDER = 0:
    • F = 0.5 × CSExtraDelay × GPMC_FCLK(17)
  • Case GPMCFCLKDIVIDER = 1:
    • F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even)
    • F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime) is a multiple of 3)
    • F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
    • F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)
(7) For ADV falling edge (ADV activated):
  • Case GPMCFCLKDIVIDER = 0:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
  • Case GPMCFCLKDIVIDER = 1:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are even)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
    • G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Reading mode:
  • Case GPMCFCLKDIVIDER = 0:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
  • Case GPMCFCLKDIVIDER = 1:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime are even)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
    • G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Writing mode:
  • Case GPMCFCLKDIVIDER = 0:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
  • Case GPMCFCLKDIVIDER = 1:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime are even)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
    • G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)
(8) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):
  • Case GPMCFCLKDIVIDER = 0:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(17)
  • Case GPMCFCLKDIVIDER = 1:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even)
    • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime) is a multiple of 3)
    • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
    • H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)

For OE rising edge (OE deactivated):
  • Case GPMCFCLKDIVIDER = 0:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(17)
  • Case GPMCFCLKDIVIDER = 1:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even)
    • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime) is a multiple of 3)
    • H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
    • H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)
(9) For WE falling edge (WE activated):
  • Case GPMCFCLKDIVIDER = 0:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK(17)
  • Case GPMCFCLKDIVIDER = 1:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are even)
    • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime) is a multiple of 3)
    • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
    • I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)

For WE rising edge (WE deactivated):
  • Case GPMCFCLKDIVIDER = 0:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK (17)
  • Case GPMCFCLKDIVIDER = 1:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are even)
    • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime) is a multiple of 3)
    • I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
    • I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
(10) J = GPMC_FCLK(17)
(11) First transfer only for CLK DIV 1 mode.
(12) Half cycle; for all data after initial transfer for CLK DIV 1 mode.
(13) Half cycle of GPMC_CLKOUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLKOUT divide down from GPMC_FCLK.
(14) In GPMC_CSn[i], i is equal to 0, 1, 2, or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
(15) P = GPMC_CLK period in ns
(16) For read: K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
(17) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(18) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the GPMC_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER.
(19) For div_by_1_mode:
  • GPMC_CONFIG1_i register: GPMCFCLKDIVIDER = 0h:
    • GPMC_CLK frequency = GPMC_FCLK frequency

  • CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100 MHz

  • GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)

For no extra_delay:
  • GPMC_CONFIG2_i Register: CSEXTRADELAY = 0h = CSn Timing control signal is not delayed
  • GPMC_CONFIG4_i Register: WEEXTRADELAY = 0h = nWE timing control signal is not delayed
  • GPMC_CONFIG4_i Register: OEEXTRADELAY = 0h = nOE timing control signal is not delayed
  • GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed
(20) For 100 MHz:
  • CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = MAIN_PLL2_HSDIV1_CLKOUT / 3
For 133 MHz:
  • CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT
AM69A AM69 GPMC and NOR Flash — Synchronous Single Read (GPMCFCLKDIVIDER = 0)
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 6-51 GPMC and NOR Flash — Synchronous Single Read (GPMCFCLKDIVIDER = 0)
AM69A AM69 GPMC and NOR Flash — Synchronous Burst Read — 4x16–bit (GPMCFCLKDIVIDER = 0)
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 6-52 GPMC and NOR Flash — Synchronous Burst Read — 4x16–bit (GPMCFCLKDIVIDER = 0)
AM69A AM69 GPMC and NOR Flash—Synchronous Burst Write (GPMCFCLKDIVIDER = 0)
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 6-53 GPMC and NOR Flash—Synchronous Burst Write (GPMCFCLKDIVIDER = 0)
AM69A AM69 GPMC and Multiplexed NOR Flash — Synchronous Burst Read
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 6-54 GPMC and Multiplexed NOR Flash — Synchronous Burst Read
AM69A AM69 GPMC and Multiplexed NOR Flash — Synchronous Burst Write
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 6-55 GPMC and Multiplexed NOR Flash — Synchronous Burst Write