SBASAY6 December 2024 AMC0236
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
If the high-side supply (AVDD) is missing, the device provides a constant bitstream of logic 0's at the output, and DOUT is permanently low. Figure 7-6 shows a timing diagram of this process. A one is not generated every 128 clock pulses, which differentiates this condition from a valid negative fullscale input. This feature helps identify high-side power-supply problems on the board. See the Diagnosing Delta-Sigma Modulator Bitstream Using C2000™ Configurable Logic Block (CLB) application note for code examples of diagnosing the digital bitstream.