SBASAZ5 October   2024 AMC0386-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5.   Device Comparison Table
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagrams
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Input
      2. 6.3.2 Modulator
      3. 6.3.3 Isolation Channel Signal Transmission
      4. 6.3.4 Digital Output
        1. 6.3.4.1 Output Behavior in Case of a Fullscale Input
        2. 6.3.4.2 Output Behavior in Case of a Missing High-Side Supply
    4. 6.4 Device Functional Modes
  9. 7 Application and Implementation
    1. 7.1 Best Design Practices
    2. 7.2 Power Supply Recommendations
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DFX|15
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.2 Modulator

Figure 6-1 conceptualizes the second-order, switched-capacitor, feed-forward ΔΣ modulator implemented in the AMC0386-Q1. The output V5 of the 1-bit, digital-to-analog converter (DAC) is subtracted from the input voltage VIN = (VSNSP – VSNSN). This subtraction provides an analog voltage V1 at the input of the first integrator stage. The output of the first integrator feeds the input of the second integrator stage. The result or the second integration is an output voltage V3 that is summed with the input signal VIN and the output of the first integrator V2. Depending on the value of the resulting voltage V4, the output of the comparator is changed. In this case, the 1-bit DAC responds on the next clock pulse by changing the associated analog output voltage V5. Thus, causing the integrators to progress in the opposite direction and forcing the integrator output value to track the average value of the input.

AMC0386-Q1 Block Diagram of a Second-Order Modulator Figure 6-1 Block Diagram of a Second-Order Modulator