SBAS562B April   2012  – December 2019 AMC1100

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Descriptions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Insulation Characteristics Curves
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 The AMC1100 in Frequency Inverters
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 The AMC1100 in Energy Metering
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 Isolation Glossary
          1. 11.1.1.1.1 Insulation:
          2. 11.1.1.1.2 Pollution Degree:
          3. 11.1.1.1.3 Installation Category:
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Insulation Specifications

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance(1) Shortest pin-to-pin distance through air, DUB package ≥ 7 mm
Shortest pin-to-pin distance through air, DWV package ≥ 8.5
CPG External creepage(1) Shortest pin-to-pin distance across the package surface, DUB package ≥ 7 mm
Shortest pin-to-pin distance across the package surface, DWV package ≥ 8.5
DTI Distance through insulation Minimum internal gap (internal clearance) of the insulation ≥ 0.014 mm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112, DUB package ≥ 400 V
DIN EN 60112 (VDE 0303-11); IEC 60112, DWV package ≥ 600
Material group According to IEC 60664-1, DUB package II
According to IEC 60664-1, DWV package I
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 300 VRMS I-IV
Rated mains voltage ≤ 600 VRMS I-III
DIN VDE V 0884-11: 2017-01(2)
VIORM Maximum repetitive peak isolation voltage At ac voltage (bipolar) 1200 VPK
VIOWM Maximum-rated isolation working voltage At ac voltage (sine wave) 849 VRMS
At dc voltage 1200 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification test) 4250 VPK
VTEST = 1.2 × VIOTM, t = 1 s (100% production test) 5100
VIOSM Maximum surge isolation voltage(3) Test method per IEC 60065, 1.2/50-µs waveform,
VTEST = 1.3 × VIOSM = 6000 VPK (qualification)		 4615 VPK
qpd Apparent charge(4) Method a, after input/output safety test subgroup 2 / 3,
Vini = VIOTM, tini = 60 s,
Vpd(m) = 1.2 × VIORM = 1440 VPK, tm = 10 s		 ≤ 5 pC
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s,
Vpd(m) = 1.3 × VIORM = 1560 VPK, tm = 10 s		 ≤ 5
Method b1, at routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s,
Vpd(m) = 1.5 × VIORM = 1800 VPK, tm = 1 s		 ≤ 5
CIO Barrier capacitance, input to output(5) VIO = 0.5 VPP at 1 MHz 1.2 pF
RIO Insulation resistance, input to output(5) VIO = 500 V at TA < 85°C > 1012 Ω
VIO = 500 V at 85°C < TA < 105°C > 1011
VIO = 500 V at TS = 150°C > 109
Pollution degree 2
Climatic category 40/125/21
UL1577
VISO Withstand isolation voltage VTEST = VISO = 3005 VRMS or 4250 VDC, t = 60 s (qualification), VTEST = 1.2 × VISO = 3606 VRMS, t = 1 s (100% production test) 3005 VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves and ribs on the PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier are tied together, creating a two-pin device.