SBASAH9 February 2022 AMC1306M25-Q1
PRODUCTION DATA
Figure 7-2 conceptualizes the second-order, switched-capacitor, feed-forward ΔΣ modulator implemented in the AMC1306M25-Q1. The analog input voltage VIN and the output V5 of the 1-bit digital-to-analog converter (DAC) are differentiated, providing an analog voltage V1 at the input of the first integrator stage. The output of the first integrator feeds the input of the second integrator stage, resulting in output voltage V3 that is differentiated with the input signal VIN and the output of the first integrator V2. Depending on the polarity of the resulting voltage V4, the output of the comparator is changed. In this case, the 1-bit DAC responds on the next clock pulse by changing the associated analog output voltage V5, causing the integrators to progress in the opposite direction, and forcing the value of the integrator output to track the average value of the input.
The modulator shifts the quantization noise to high frequencies, as illustrated in Figure 7-1. Therefore, use a low-pass digital filter at the output of the device to increase the overall performance. This filter is also used to convert the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's C2000™ and Sitara™ microcontroller families offer a suitable programmable, hardwired filter structure termed a sigma-delta filter module (SDFM) optimized for usage with the AMC1306M25-Q1. Alternatively, a field-programmable gate array (FPGA) or complex programmable logic device (CPLD) can be used to implement the filter.