SBASAO0A May 2023 – September 2023 AMC130M03
PRODUCTION DATA
An LVCMOS clock must be provided at the CLKIN pin continuously when the AMC130M03 is running in normal operation. The frequency of the clock can be scaled in conjunction with the power mode to provide a tradeoff between power consumption and dynamic range.
The PWR[1:0] bits in the CLOCK register allow the device to be configured in one of two power modes: high-resolution (HR) or low-power (LP) mode. Changing the PWR[1:0] bits scales the internal bias currents to achieve the expected power levels. The external clock frequency must follow the guidance provided in the Recommended Operating ConditionsRecommended Operating Conditions table corresponding to the intended power mode for the device to perform according to the specification.
The main clock must be externally provided at the CLKIN pin. As shown in Figure 8-5, a user-programmable clock divider divides the main clock to derive the internal modulator clock (MOD_CLK). By default, the main clock provided at the CLKIN pin is divided by NDIV = 2 to generate a 50% duty cycle internal modulator clock. As listed in Table 8-8, the divider ratio NDIV can be changed to values of 4, 8, and 12 using the CLK_DIV[1:0] bits in the CLOCK register.
CLK_DIV[1:0] | NDIV FOR MOD_CLK AT ALL CHANNELS |
---|---|
00b | 2 |
01b | 4 |
10b | 8 |
11b | 12 |
The clock frequency range of the internal DC/DC converter must be synchronized with the modulator clock to minimize interference. To optimize the DC/DC converter internal clock, the actual frequency value of the modulator clock must be written to the DCDC_CTRL register immediately after device power-up. The modulator clock frequency is a result of the frequency provided at the CLKIN pin and the selected divider ratio (for example, if a 4-MHz clock frequency is provided at the CLKIN pin, and the divider ratio is set to 4, then the frequency of the modulator clock MOD_CLK is 1 MHz). The correct modulator clock frequency value must be configured in the DCDC_CTRL register, as given in Table 8-3, by writing to the DCDC_FREQ[3:0] register bits immediately after start-up.
An example calculation is:
MODULATOR CLOCK FREQUENCY (MHz) | DCDC_FREQ[3:0] BIT SETTING |
---|---|
3.768 MHz to 4.100 MHz | 0000b |
3.366 MHz to 3.768 MHz | 0001b |
3.041 MHz to 3.366 MHz | 0010b |
2.773 MHz to 3.041 MHz | 0011b |
2.549 MHz to 2.773 MHz | 0100b |
2.358 MHz to 2.549 MHz | 0101b |
2.194 MHz to 2.358 MHz | 0110b |
2.051 MHz to 2.194 MHz | 0111b |
1.926 MHz to 2.051 MHz | 1000b |
1.815 MHz to 1.926 MHz | 1001b |
1.716 MHz to 1.815 MHz | 1010b |
1.627 MHz to 1.716 MHz | 1011b |
1.547 MHz to 1.627 MHz | 1100b |
1.475 MHz to 1.547 MHz | 1101b |
1.409 MHz to 1.475 MHz | 1110b |
1.400 MHz to 1.409 MHz | 1111b |