SBASAO0A May 2023 – September 2023 AMC130M03
PRODUCTION DATA
The modulator clock MOD_CLK for each ADC is derived from the external clock provided at the CLKIN pin by a user-controlled programmable clock divider, as described in the Clocking and Power Modes section. By default, the clock provided at the CLKIN pin is divided by NDIV = 2 to generate a 50% duty cycle internal modulator clock MOD_CLK. The divider ratio NDIV can be changed to values of 4, 8, and 12 using the CLK_DIV[1:0] bits in the CLOCK register.
When in temperature sensor mode, MOD_CLK is further divided by a factor of 32 and used as the modulator clock for channel 2 that converts the temperature readings on channel 2. However, the modulators on channel 0 and channel 1 are still controlled by the undivided MOD_CLK, as defined by the CLK_DIV[1:0] bits in the CLOCK register.
Table 8-8 shows the MOD_CLK for each ADC channel when operating in temperature sensor mode and in normal mode.
TS_EN | CLK_DIV[1:0] | NDIV FOR MOD_CLK | ||
---|---|---|---|---|
CHANNEL 0 | CHANNEL 1 | CHANNEL 2 | ||
AIN0N, AIN0P | AIN12N, AIN1P | AIN12N, AIN2P | ||
0b | 00b | 2 | 2 | 2 |
0b | 01b | 4 | 4 | 4 |
0b | 10b | 8 | 8 | 8 |
0b | 11b | 12 | 12 | 12 |
1b | 00b | 2 | 2 | 64 |
1b | 01b | 4 | 4 | 128 |
1b | 10b | 8 | 8 | 256 |
1b | 11b | 12 | 12 | 384 |
As explained in the Temperature Sensor section, the ADC conversion rate is reduced for the temperature sensor mode by a factor 32.