SBASAO0A May 2023 – September 2023 AMC130M03
PRODUCTION DATA
Each channel of the AMC130M03 features an integrated programmable gain amplifier (PGA) that provides gains of 1, 2, 4, 8, 16, 32, 64, and 128. The gains for all channels are individually controlled by the PGAGAINx[2:0] bits for each channel in the GAIN register.
Changing the PGA gain scales the differential full-scale input voltage range (FSR) of the ADC. Equation 2 describes the relationship between FSR and gain. Equation 2 uses the internal reference voltage, 1.2 V, as the scaling factor without accounting for gain error caused by tolerance in the reference voltage.
Table 8-1 shows the corresponding full-scale ranges for each gain setting.
GAIN SETTING | FSR |
---|---|
1 | ±1.2 V |
2 | ±600 mV |
4 | ±300 mV |
8 | ±150 mV |
16 | ±75 mV |
32 | ±37.5 mV |
64 | ±18.75 mV |
128 | ±9.375 mV |
The input impedance of the PGA dominates the input impedance characteristics of the AMC130M03. The PGA input impedance for gain settings up to 4 behaves according to Equation 3 without accounting for device tolerance and change over temperature. Minimize the output impedance of the circuit that drives the AMC130M03 inputs to obtain the best possible gain error, INL, and distortion performance.
where:
By default, NDIV = 2. NDIV is set by the programmable clock divider, see the Clocking and Power Modes section.
The device uses an input precharge buffer for PGA gain settings of 8 and higher. The input impedance at these gain settings is very high. Specifying the input bias current for these gain settings is therefore more useful.