SBASA56 September 2023 AMC131M02
PRODUCTION DATA
Table 8-13 lists the memory-mapped registers for the AMC131M02 registers. All register offset addresses not listed in Table 8-13 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Reset | Bit 15 | Bit 14 | Bit 13 | Bit 12 | Bit 11 | Bit 10 | Bit 9 | Bit 8 |
---|---|---|---|---|---|---|---|---|---|---|
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | |||
00h | ID | Xb | RESERVED | CHANCNT[3:0] | ||||||
RESERVED | ||||||||||
01h | STATUS | 0540h | LOCK | F_RESYNC | REG_MAP | CRC_ERR | CRC_TYPE | RESET | WLENGTH[1:0] | |
FUSE_FAIL | SEC_FAIL | RESERVED | DRDY1 | DRDY0 | ||||||
02h | MODE | 0510h | RESERVED | REG_CRC_EN | RX_CRC_EN | CRC_TYPE | RESET | WLENGTH[1:0] | ||
RESERVED | TIMEOUT | DRDY_SEL[1:0] | DRDY_HiZ | DRDY_FMT | ||||||
03h | CLOCK | 030Eh | RESERVED | CH1_EN | CH0_EN | |||||
CLK_DIV[1:0] | TURBO | OSR[2:0] | PWR[1:0] | |||||||
04h | GAIN | 0000h | RESERVED | |||||||
RESERVED | PGAGAIN1[2:0] | RESERVED | PGAGAIN0[2:0] | |||||||
06h | CFG | 0600h | RESERVED | GPO_EN | GPO_DAT | GC_DLY[3:0] | GC_EN | |||
RESERVED | ||||||||||
09h | CH0_CFG | 0000h | PHASE0[9:0] | |||||||
PHASE0[9:0] | RESERVED | MUX0[1:0] | ||||||||
0Ah | CH0_OCAL_MSB | 0000h | OCAL0_MSB[15:0] | |||||||
OCAL0_MSB[15:0] | ||||||||||
0Bh | CH0_OCAL_LSB | 0000h | OCAL0_LSB[7:0] | |||||||
RESERVED | ||||||||||
0Ch | CH0_GCAL_MSB | 8000h | GCAL0_MSB[15:0] | |||||||
GCAL0_MSB[15:0] | ||||||||||
0Dh | CH0_GCAL_LSB | 0000h | GCAL0_LSB[7:0] | |||||||
RESERVED | ||||||||||
0Eh | CH1_CFG | 0000h | PHASE1[9:0] | |||||||
PHASE1[9:0] | RESERVED | MUX1[1:0] | ||||||||
0Fh | CH1_OCAL_MSB | 0000h | OCAL1_MSB[15:0] | |||||||
OCAL1_MSB[15:0] | ||||||||||
10h | CH1_OCAL_LSB | 0000h | OCAL1_LSB[7:0] | |||||||
RESERVED | ||||||||||
11h | CH1_GCAL_MSB | 8000h | GCAL1_MSB[15:0] | |||||||
GCAL1_MSB[15:0] | ||||||||||
12h | CH1_GCAL_LSB | 0000h | GCAL1_LSB[7:0] | |||||||
RESERVED | ||||||||||
31h | DCDC_CTRL | 0000h | RESERVED | DCDC_FREQ[3:0] | ||||||
RESERVED | DCDC_EN | |||||||||
3Eh | REGMAP_CRC | 0000h | REG_CRC[15:0] | |||||||
REG_CRC[15:0] |
Complex bit access types are encoded to fit into small table cells. Table 8-14 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CHANCNT[3:0] | ||||||
R-0010b | R-0010b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R | 0010b | Reserved Always reads 0010b |
11:8 | CHANCNT[3:0] | R | 0010b | Channel count Always reads 0010b |
7:0 | RESERVED | R | X | Reserved Values are subject to change without notice. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
LOCK | F_RESYNC | REG_MAP | CRC_ERR | CRC_TYPE | RESET | WLENGTH[1:0] | |
R-0b | R-0b | R-0b | R-0b | R-0b | R-1b | R-01b | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FUSE_FAIL | SEC_FAIL | RESERVED | DRDY1 | DRDY0 | |||
R-0b | R-1b | R-0000b | R-0b | R-0b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | LOCK | R | 0b | SPI interface lock indicator Indicates the SPI interface is locked by the lock command. The bit is reset to 0b by the unlock command. 0b = Unlocked 1b = Locked |
14 | F_RESYNC | R | 0b | ADC resynchronization indicator This bit is set each time the ADC resynchronizes. This bit is cleared by reading the STATUS register, either by executing the NULL command or a RREG command accessing the STATUS register. 0b = No resynchronization occurred 1b = Resynchronization occurred |
13 | REG_MAP | R | 0b | Register map CRC fault indicator Indicates a register map CRC fault occurred. This bit is cleared by reading the STATUS register, either by executing the NULL command or a RREG command accessing the STATUS register. 0b = No register map CRC fault occurred 1b = Register map CRC fault occurred |
12 | CRC_ERR | R | 0b | SPI input CRC error indicator Indicates a SPI input CRC fault occurred. This bit is cleared by reading the STATUS register, either by executing the NULL command or a RREG command accessing the STATUS register. 0b = No CRC error 1b = Input CRC error occurred |
11 | CRC_TYPE | R | 0b | CRC type indicator Indicates the CRC type. This bit is cleared by a device reset. 0b = 16-bit CCITT 1b = 16-bit ANSI |
10 | RESET | R | 1b | Reset status indicator The device reset indicator is triggered by the RESET pin, power-on-reset or the RESET command. This bit is cleared by writing 0b to the RESET bit in the MODE register. 0b = Not reset 1b = Reset occurred |
9:8 | WLENGTH[1:0] | R | 01b | Data word length indicator Indicates the data word frame length. This bit is cleared by a device reset. 00b = 16 bit 01b = 24 bits 10b = 32 bits; zero padding 11b = 32 bits; MSB sign extension |
7 | FUSE_FAIL | R | 0b | Fuse parity fault indicator Indicates a fault of the internal memory. This bit is cleared by reading the STATUS register, either by executing the NULL command or a RREG command accessing the STATUS register. If the physical fault persists, the indicator is set again automatically. 0b = Fuse parity OK 1b = Fuse parity not OK |
6 | SEC_FAIL | R | 1b | High-side supply fault indicator Indicates a fault of the high-side output of the DC/DC converter, or a communication error during the data transmission across the isolation barrier. This bit is cleared by reading the STATUS register, either by executing the NULL command or a RREG command accessing the STATUS register. 0b = High-side supply OK 1b = High-side supply not OK |
5:2 | RESERVED | R | 0000b | Reserved Always reads 0000b |
1 | DRDY1 | R | 0b | Channel 1 ADC data available indicator 0b = No new data available 1b = New data are available |
0 | DRDY0 | R | 0b | Channel 0 ADC data available indicator 0b = No new data available 1b = New data are available |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | REG_CRC_EN | RX_CRC_EN | CRC_TYPE | RESET | WLENGTH[1:0] | ||
R/W-00b | R/W-0b | R/W-0b | R/W-0b | R/W-1b | R/W-01b | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | DRDY_SEL[1:0] | DRDY_HiZ | DRDY_FMT | |||
R/W-000b | R/W-1b | R/W-00b | R/W-0b | R/W-0b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | RESERVED | R/W | 00b | Reserved Always write 00b |
13 | REG_CRC_EN | R/W | 0b | Register map CRC enable 0b = Disabled 1b = Enabled |
12 | RX_CRC_EN | R/W | 0b | SPI input CRC enable 0b = Disabled 1b = Enabled |
11 | CRC_TYPE | R/W | 0b | SPI input and output, register map CRC type 0b = 16-bit CCITT 1b = 16-bit ANSI |
10 | RESET | R/W | 1b | Reset Write 0b to clear the RESET bit in the STATUS register 0b = No reset 1b = Reset occurred |
9:8 | WLENGTH[1:0] | R/W | 01b | Data word length selection 00b = 16 bits 01b = 24 bits 10b = 32 bits; LSB zero padding 11b = 32 bits; MSB sign extension |
7:5 | RESERVED | R/W | 000b | Reserved Always write 000b |
4 | TIMEOUT | R/W | 1b | SPI timeout enable 0b = Disabled 1b = Enabled |
3:2 | DRDY_SEL[1:0] | R/W | 00b | DRDY pin signal source selection 00b = Most lagging enabled channel 01b = Logic OR of all the enabled channels 10b = Most leading enabled channel 11b = Most leading enabled channel |
1 | DRDY_HiZ | R/W | 0b | DRDY pin state when conversion data are not available 0b = Logic high 1b = High impedance |
0 | DRDY_FMT | R/W | 0b | DRDY signal format when conversion data are available 0b = Logic low 1b = Low pulse with a fixed duration |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CH1_EN | CH0_EN | |||||
R/W-000000b | R/W-1b | R/W-1b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLK_DIV[1:0] | TURBO | OSR[2:0] | PWR[1:0] | ||||
R/W-00b | R/W-0b | R/W-011b | R/W-10b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:10 | RESERVED | R/W | 000000b | Reserved Always write 000000b |
9 | CH1_EN | R/W | 1b | Channel 1 ADC enable 0b = Disabled 1b = Enabled |
8 | CH0_EN | R/W | 1b | Channel 0 ADC enable 0b = Disabled 1b = Enabled |
7:6 | CLK_DIV[1:0] | R/W | 00b | Clock divider ratio selection 00b = Divide by 2 01b = Divide by 4 10b = Divide by 8 11b = Divide by 12 |
5 | TURBO | R/W | 0b | Turbo mode (OSR = 64) Selects oversampling ratio 64 by setting this bit to 1b. The OSR[2:0] bits are ignored if this bit is set to 1b. 0b = Disabled 1b = Enabled |
4:2 | OSR[2:0] | R/W | 011b | Modulator oversampling ratio selection 000b = 128 001b = 256 010b = 512 011b = 1024 100b = 2048 101b = 4096 110b = 8192 111b = 16384 |
1:0 | PWR[1:0] | R/W | 10b | Power mode selection 00b = Reserved. Do not use. 01b = Low power 10b = High resolution 11b = Reserved. Do not use. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PGAGAIN1[2:0] | RESERVED | PGAGAIN0[2:0] | ||||
R/W-0b | R/W-000b | R/W-0b | R/W-000b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | RESERVED | R/W | 00000000b | Always write 00000000b |
7 | RESERVED | R/W | 0b | Always write 0b |
6:4 | PGAGAIN1[2:0] | R/W | 000b | PGA gain selection for channel 1 000b = 1 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128 |
3 | RESERVED | R/W | 0b | Reserved Always write 0b |
2:0 | PGAGAIN0[2:0] | R/W | 000b | PGA gain selection for channel 0 000b = 1 001b = 2 010b = 4 011b = 8 100b = 16 101b = 32 110b = 64 111b = 128 |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | GPO_EN | GPO_DAT | GC_DLY[3:0] | GC_EN | |||
R/W-0b | R/W-0b | R/W-0b | R/W-0011b | R/W-0b | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R/W-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R/W | 0b | Reserved Always write 0b |
14 | GPO_EN | R/W | 0b | Digital output enable Enables digital output (GPO) functionality at AIN2P pin. 0b = Digital output disabled 1b = Digital output enabled |
13 | GPO_DAT | R/W | 0b | Digital output data Digital output (GPO) data if GPO_EN = 1b. 0b = Zero output 1b = One output |
12:9 | GC_DLY[3:0] | R/W | 0011b | Global-chop delay selection Delay in modulator clock periods before measurement begins. 0000b = 2 0001b = 4 0010b = 8 0011b = 16 0100b = 32 0101b = 64 0110b = 128 0111b = 256 1000b = 512 1001b = 1024 1010b = 2048 1011b = 4096 1100b = 8192 1101b = 16384 1110b = 32768 1111b = 65536 |
8 | GC_EN | R/W | 0b | Global-chop enable 0b = Disabled 1b = Enabled |
7:0 | RESERVED | R/W | 00000000b | Reserved Always write 00000000b |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PHASE0[9:0] | |||||||
R/W-0000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHASE0[9:0] | RESERVED | MUX0[1:0] | |||||
R/W-0000000000b | R-0000b | R/W-00b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:6 | PHASE0[9:0] | R/W | 0000000000b | Channel 0 phase delay selection Phase delay in modulator clock cycles provided in twos complement format. |
5:2 | RESERVED | R | 0000b | Reserved Always reads 0000b |
1:0 | MUX0[1:0] | R/W | 00b | Channel 0 input selection Input multiplexer for channel 0 00b = AIN0P and AIN0N 01b = AIN0 disconnected (ADC inputs shorted) 10b = DC diagnostic signal 11b = AC diagnostic signal |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCAL0_MSB[15:0] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OCAL0_MSB[15:0] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | OCAL0_MSB[15:0] | R/W | 0000000000000000b | Channel 0 offset calibration register bits [23:8] Value provided in twos complement format. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCAL0_LSB[7:0] | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | OCAL0_LSB[7:0] | R/W | 00000000b | Channel 0 offset calibration register bits [7:0] Value provided in twos complement format. |
7:0 | RESERVED | R | 00000000b | Reserved Always reads 00000000b |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GCAL0_MSB[15:0] | |||||||
R/W-1000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GCAL0_MSB[15:0] | |||||||
R/W-1000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | GCAL0_MSB[15:0] | R/W | 1000000000000000b | Channel 0 gain calibration register bits [23:8] Unsigned number for the gain range from 0.0 to 2.0 x (224 – 1) / 224 |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GCAL0_LSB[7:0] | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | GCAL0_LSB[7:0] | R/W | 00000000b | Channel 0 gain calibration register bits [7:0] Unsigned number for the gain range from 0.0 to 2.0 x (224 – 1) / 224 |
7:0 | RESERVED | R | 00000000b | Reserved Always reads 00000000b |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PHASE1[9:0] | |||||||
R/W-0000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHASE1[9:0] | RESERVED | MUX1[1:0] | |||||
R/W-0000000000b | R-0000b | R/W-00b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:6 | PHASE1[9:0] | R/W | 0000000000b | Channel 1 phase delay selection Phase delay in modulator clock cycles provided in twos complement format. |
5:2 | RESERVED | R | 0000b | Reserved Always reads 0000b |
1:0 | MUX1[1:0] | R/W | 00b | Channel 1 input selection Input multiplexer for channel 1 00b = AIN1P and AIN1N 01b = AIN1 disconnected (ADC inputs shorted) 10b = DC diagnostic signal 11b = AC diagnostic signal |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCAL1_MSB[15:0] | |||||||
R/W-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OCAL1_MSB[15:0] | |||||||
R/W-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | OCAL1_MSB[15:0] | R/W | 0000000000000000b | Channel 1 offset calibration register bits [23:8] Value provided in twos complement format. |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OCAL1_LSB[7:0] | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | OCAL1_LSB[7:0] | R/W | 00000000b | Channel 1 offset calibration register bits [7:0] Value provided in twos complement format. |
7:0 | RESERVED | R | 00000000b | Reserved Always reads 00000000b |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GCAL1_MSB[15:0] | |||||||
R/W-1000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GCAL1_MSB[15:0] | |||||||
R/W-1000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | GCAL1_MSB[15:0] | R/W | 1000000000000000b | Channel 1 gain calibration register bits [23:8] Unsigned number for the gain range from 0.0 to 2.0 x (224 – 1) / 224 |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GCAL1_LSB[7:0] | |||||||
R/W-00000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | GCAL1_LSB[7:0] | R/W | 00000000b | Channel 1 gain calibration register bits [7:0] Unsigned number for the gain range from 0.0 to 2.0 x (224 – 1) / 224 |
7:0 | RESERVED | R | 00000000b | Reserved Always reads 00000000b |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DCDC_FREQ[3:0] | ||||||
R/W-0000b | R/W-0000b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DCDC_EN | ||||||
R/W-0000000b | R/W-0b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:12 | RESERVED | R/W | 0000b | Reserved Always write 0000b |
11:8 | DCDC_FREQ[3:0] | R/W | 0000b | DC/DC frequency range selection Selects the range of the modulator clock frequency, based on the frequency at the CLKIN pin and clock divider ratio. 0000b = 3.76 MHz to 4.10 MHz 0001b = 3.52 MHz to 3.84 MHz 0010b = 3.30 MHz to 3.59 MHz 0011b = 3.09 MHz to 3.36 MHz 0100b = 2.89 MHz to 3.15 MHz 0101b = 2.71 MHz to 2.95 MHz 0110b = 2.53 MHz to 2.76 MHz 0111b = 2.37 MHz to 2.59 MHz 1000b = 2.22 MHz to 2.42 MHz 1001b = 2.08 MHz to 2.27 MHz 1010b = 1.95 MHz to 2.12 MHz 1011b = 1.82 MHz to 1.99 MHz 1100b = 1.71 MHz to 1.86 MHz 1101b = 1.60 MHz to 1.74 MHz 1110b = 1.50 MHz to 1.63 MHz 1111b = 1.40 MHz to 1.53 MHz |
7:1 | RESERVED | R/W | 0000000b | Reserved Always write 0000000b |
0 | DCDC_EN | R/W | 0b | DC/DC enable Enables the integrated DC/DC converter. 0b = Disabled 1b = Enabled |
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
REG_CRC[15:0] | |||||||
R-0000000000000000b | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REG_CRC[15:0] | |||||||
R-0000000000000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | REG_CRC[15:0] | R | 0000000000000000b | Register map CRC value |