SBASA56 September   2023 AMC131M02

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Insulation Specifications
    6. 6.6  Safety-Related Certifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Isolated DC/DC Converter
        1. 8.3.1.1 DC/DC Converter Failure Detection
      2. 8.3.2  High-Side Current Drive Capability
      3. 8.3.3  Isolation Channel Signal Transmission
      4. 8.3.4  Input ESD Protection Circuitry
      5. 8.3.5  Input Multiplexer
      6. 8.3.6  Programmable Gain Amplifier (PGA)
      7. 8.3.7  Voltage Reference
      8. 8.3.8  Internal Test Signals
      9. 8.3.9  Clocking and Power Modes
      10. 8.3.10 ΔΣ Modulator
      11. 8.3.11 Digital Filter
        1. 8.3.11.1 Digital Filter Implementation
          1. 8.3.11.1.1 Fast-Settling Filter
          2. 8.3.11.1.2 SINC3 and SINC3 + SINC1 Filter
        2. 8.3.11.2 Digital Filter Characteristic
      12. 8.3.12 Channel Phase Calibration
      13. 8.3.13 Calibration Registers
      14. 8.3.14 Register Map CRC
      15. 8.3.15 General-Purpose Digital Output (GPO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Start-Up Behavior After Power-Up
      3. 8.4.3 Start-Up Behavior After a Pin Reset or RESET Command
      4. 8.4.4 Start-Up Behavior After a Pause in CLKIN
      5. 8.4.5 Synchronization
      6. 8.4.6 Conversion Modes
        1. 8.4.6.1 Continuous-Conversion Mode
        2. 8.4.6.2 Global-Chop Mode
      7. 8.4.7 Power Modes
      8. 8.4.8 Standby Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  Conversion Synchronization or System Reset (SYNC/RESET)
        7. 8.5.1.7  SPI Communication Frames
        8. 8.5.1.8  SPI Communication Words
        9. 8.5.1.9  Short SPI Frames
        10. 8.5.1.10 Communication Cyclic Redundancy Check (CRC)
        11. 8.5.1.11 SPI Timeout
      2. 8.5.2 ADC Conversion Data
      3. 8.5.3 Commands
        1. 8.5.3.1 NULL (0000 0000 0000 0000)
        2. 8.5.3.2 RESET (0000 0000 0001 0001)
        3. 8.5.3.3 STANDBY (0000 0000 0010 0010)
        4. 8.5.3.4 WAKEUP (0000 0000 0011 0011)
        5. 8.5.3.5 LOCK (0000 0101 0101 0101)
        6. 8.5.3.6 UNLOCK (0000 0110 0101 0101)
        7. 8.5.3.7 RREG (101a aaaa annn nnnn)
          1. 8.5.3.7.1 Reading a Single Register
          2. 8.5.3.7.2 Reading Multiple Registers
        8. 8.5.3.8 WREG (011a aaaa annn nnnn)
      4. 8.5.4 ADC Output Buffer and FIFO Buffer
      5. 8.5.5 Collecting Data for the First Time or After a Pause in Data Collection
    6. 8.6 AMC131M02 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Antialiasing
      3. 9.1.3 Minimum Interface Connections
      4. 9.1.4 Multiple Device Configuration
      5. 9.1.5 Calibration
      6. 9.1.6 Troubleshooting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Voltage Measurement
        2. 9.2.2.2 Current Shunt Measurement
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C and DVDD = 3.0 V to 5.5V; typical specifications are at TA = 25°C, DVDD = 3.3 V, and for channel 0; all specifications are at fCLKIN = 8.192 MHz, data rate = 4 kSPS, high-resolution mode, all channels enabled, global-chop mode disabled, and gain = 1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
IIB Input bias current AINxP = AINxN = HGND;
IIB = (IIBP + IIBN) / 2, Gain = 1, 2, or 4		 0.65 0.9 μA
AINxP = AINxN = HGND;
IIB = (IIBP + IIBN) / 2, Gain = 8 to 128		 –1.0 –0.65
TCIIB Input bias current drift –1  ±0.35 1 (2) nA/°C
IIO Input offset current IIO = IIBP – IIBN ±15 nA
RIN Single-ended input impedance AINxN = HGND, gain = 1, 2, or 4 250 kΩ
AINxN = HGND, gain = 8 to 128 0.5 MΩ
ZIND Differential input impedance (AINxN + AINxP) / 2 = HGND,
Gain = 1, 2, or 4		 275 kΩ
(AINxN + AINxP) / 2 = HGND,
Gain = 8 to 128		 1 MΩ
ADC CHARACTERISTICS
Resolution 24 Bits
Gain settings 1, 2, 4, 8, 16, 32, 64, 128
fDATA Data rate High-resolution mode, fCLKIN = 8.192 MHz,
NDIV = 2		 250 64k SPS
Low-power mode, fCLKIN = 4.096 MHz,
NDIV = 2		 125 32k
SPI start-up time Measured from supplies at 90% to SPI interface ready to accept data 0.3 ms
Converter start-up time Measured from DCDC enable bit set to first DRDY falling edge with data settled to 0.1% (CLKIN running) 1.0 ms
ADC PERFORMANCE
INL Integral nonlinearity End-point fit 6 ppm of FSR
EO Offset error (input referred) External short, TA = 25°C –100 ±100 330 µV
Global-chop mode,
default global-chop delay, external short,
TA = 25°C 		–100 6 100
TCEO Offset error drift vs temperature External short –0.5 ±0.1 0.5 (3) µV/°C
Global-chop mode, external short –0.3 ±0.1 0.3 (3)
EG Gain error Channel 0, TA = 25°C, end-point fit –0.2 ±0.025 0.2 %
Channel 1, TA = 25°C, end-point fit –1 ±0.1 1
TCEG Gain error drift vs temperature Including internal reference error 8 25 (3) ppm/°C
CMRR Common-mode rejection ratio fIN = 0 Hz, VCM min ≤ VIN ≤ VCM max 110 dB
fIN = 50 Hz or 60 Hz,
VCM min ≤ VIN ≤ VCM max, VAINP = VAINN		 110
EN Input-referred noise 10 µVRMS
DR Dynamic range Gain = 1 98 dB
Gain = 32, channel 0 80
All other gain settings See Table 7-2
Crosstalk From one channel to any one of the other channels; fIN = 50 Hz or 60 Hz at AINxP
while AINxN = HGND 		–120 dB
SNR Signal-to-noise ratio fIN = 50 Hz or 60 Hz, gain = 1,
VIN = –0.5 dBFS, normalized		 98 dB
fIN = 50 Hz or 60 Hz, gain = 32, channel 0,
VIN = –0.5 dBFS, normalized		 80
THD Total harmonic distortion fIN = 50 Hz or 60 Hz (up to 5 harmonics),
VIN = –0.5 dBFS		 –102 –94 (3) dB
SFDR Spurious-free dynamic range fIN = 50 Hz or 60 Hz,
VIN = –0.5 dBFS		 105 dB
CMTI Common-mode transient immunity 100 150 V/ns
INTERNAL VOLTAGE REFERENCE
VREF Internal reference voltage 1.2 V
DIGITAL INPUTS/OUTPUTS
VIL Logic input level, low DGND 0.2 DVDD V
VIH Logic input level, high 0.8 DVDD DVDD V
VOL Logic output level, low IOL = –1 mA 0.2 DVDD V
VOH Logic output level, high IOH = 1 mA 0.8 DVDD V
IIN Input current DGND < VDigital Input < DVDD –1 1 µA
CIN Input capacitance 1 pF
CLOAD Output load capacitance 15 30 pF
HIGH-SIDE DIGITAL OUTPUT
RGPO High-side GPO output impedance Driving 0 100 Ω
Driving 1 115
IGPO High-side GPO load current 1 mA
POWER SUPPLY
IDVDD Low-side supply current(1) High-resolution mode 18 23 mA
Low-power mode 15.5 20
Standby mode, all channels disabled,
no clock applied		 160 210 µA
PD Power dissipation High-resolution mode 60 mW
Low-power mode, fCLKIN = 4.096 MHz 51
Standby mode, all channels disabled,
no clock applied		 525 µW
VDCDC_OUT DC/DC output voltage DCDC_OUT to HGND, all channels enabled, TA = 25°C 3.0 V
VHLDO_OUT High-side LDO output voltage HLDO_OUT to HGND, no external load,
any channel enabled		 2.6 2.9 3.2 V
HLDO_OUT to HGND, 1-mA external load on HLDO_OUT,any channel enabled 2.4 2.8 3.1
IH High-side supply current for auxiliary circuitry Load connected from HLDO_OUT to HGND 1 mA
(1) Currents measured with SPI idle.
(2) Specified by design and characterization, not production tested.