As shown in Figure 8-31, the AMC131M03-Q1 has two internal data buffers per ADC channel holding conversion data: an ADC output buffer and a FIFO buffer. Each buffer can only hold one conversion result at a time. The data output on DOUT is always from the FIFO buffer.

Figure 8-30 ADC Data Output Buffer Structure

Whenever an ADC channel generates new conversion data, the ADC output buffer for that channel is updated immediately with the new data. However, updating the FIFO buffer depends on the previous conversion data retrieval by the host. There are three scenarios:

• If conversion data (N) stored in the FIFO buffer has already been read by the host at the time that new conversion data (N+1) become available, then the FIFO buffer is updated with the new conversion data (N+1). In this case, data in both the ADC output buffer and the FIFO buffer are updated at the same time (that is, both buffers now hold the same conversion data N+1).
• If conversion data (N) stored in the FIFO buffer has not yet been read by the host when new conversion data (N+1) become available, then the FIFO buffer is not updated and still holds the previous conversion data (N), while the ADC output buffer now holds the new conversion data (N+1). In this case, data content is different between the ADC output buffer (N+1) and the FIFO buffer (N). After the host reads conversion data N from the FIFO buffer, the FIFO buffer is updated with the conversion data N+1. The host can then retrieve conversion data N+1.
• A special scenario exists if conversion data (N) stored in the FIFO buffer has not been read by the host, but two new conversion data already became available in the meantime (that is, the ADC output buffer is updated with conversion data N+2). In this case, the FIFO buffer is updated with conversion result N+2 at the same time the ADC output buffer is updated with conversion result N+2 (that is, both buffers now hold the same conversion data N+2). That means, conversion data N and N+1 are lost and cannot be retrieved by the host anymore.

Table 8-13 summarizes the ADC output buffer and FIFO buffer operation when new conversion data (N+1) are available.

The following three examples illustrate the behavior of the ADC output and FIFO buffer using a simplified notation to indicate which conversion data is stored in each buffer: [number of sample in the ADC output buffer | number of sample in the FIFO buffer].

Example 1: Host reads conversion results as soon as the results become available

• When the first conversion (result 1) completes, this result is placed both in the ADC output buffer and the FIFO buffer [1 | 1].
• If the host reads conversion result 1 immediately after the conversion completes, the content of the buffers stays at [1 | 1]. The host can read conversion result 1 from the FIFO buffer multiple times if needed before conversion result 2 completes.
• When conversion result 2 completes, the result is again placed into both the ADC output buffer and the FIFO buffer [2 | 2].
• If the host reads the result before the third conversion completes, result 2 is read out and the buffers stay at [2 | 2].

Example 2: Host misses reading one conversion result

• When the first conversion (result 1) completes, the result is placed both in the ADC output buffer and the FIFO buffer [1 | 1].
• If the host misses reading result 1 from the FIFO buffer before the second conversion completes, then the ADC output buffer holds result 2, and the FIFO buffer still holds result 1 [2 | 1].
• If the host now reads data before the third conversion completes, result 1 is read. The content of the buffers then updates to [2 | 2].
• Another conversion data read request by the host shifts out result 2 on DOUT. The buffers stay at [2 | 2].
• Now when the third conversion completes, both buffers update with result 3 [3 | 3].

Example 3: Host misses reading two consecutive conversion results

• When the first conversion (result 1) completes, the result is placed both in the ADC output buffer and the FIFO buffer [1 | 1].
• If the host misses reading result 1 from the FIFO buffer before the second conversion completes, then the ADC output buffer holds result 2, and the FIFO buffer still holds result 1 [2 | 1].
• Now if the third conversion completes and the host still did not retrieve data from the FIFO buffer, then result 3 overwrites the data in both the ADC output and FIFO buffer [3 | 3].
• In this case, both conversion result 1 and result 2 are lost and cannot be read anymore by the host.

Resulting from the internal structure of the ADC, including the ADC output buffer and the FIFO buffer, the DRDY pin behaves as described:

• If conversion data are read by the host every time new conversion data become available, then DRDY follows the format described in the Data Ready (DRDY) section, depending on the DRDY_FMT bit in the MODE register: When the DRDY_FMT bit is 0b, new data are indicated by DRDY changing from high to low and remaining low until either all conversion data are shifted out of the device, or remaining low and going high briefly before the next time DRDY transitions low. When the DRDY_FMT bit is 1b, new data are indicated by a short negative pulse on the DRDY pin.
• If the DRDY_FMT bit is 0b and the host does not read conversion data from the FIFO buffer before the next conversion completes, then DRDY remains low and goes high briefly before the next time DRDY transitions low (indicating a new conversion).
• If the DRDY_FMT bit is 1b and the host does not read conversion data from the FIFO buffer before the next conversion completes, then the device skips one DRDY pulse and does not provide another DRDY pulse until the second following instance when data are ready. Therefore, if the DRDY_FMT bit is 1b and the host does not read conversion data at all, the DRDY pin toggles at a rate which is half the conversion rate.