SBASAO3A May   2023  – September 2023 AMC131M03-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Insulation Specifications
    6. 6.6  Safety-Related Certifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Isolated DC/DC Converter
        1. 8.3.1.1 DC/DC Converter Failure Detection
      2. 8.3.2  High-Side Current Drive Capability
      3. 8.3.3  Isolation Channel Signal Transmission
      4. 8.3.4  Input ESD Protection Circuitry
      5. 8.3.5  Input Multiplexer
      6. 8.3.6  Programmable Gain Amplifier (PGA)
      7. 8.3.7  Voltage Reference
      8. 8.3.8  Internal Test Signals
      9. 8.3.9  Clocking and Power Modes
      10. 8.3.10 ΔΣ Modulator
      11. 8.3.11 Digital Filter
        1. 8.3.11.1 Digital Filter Implementation
          1. 8.3.11.1.1 Fast-Settling Filter
          2. 8.3.11.1.2 SINC3 and SINC3 + SINC1 Filter
        2. 8.3.11.2 Digital Filter Characteristic
      12. 8.3.12 Channel Phase Calibration
      13. 8.3.13 Calibration Registers
      14. 8.3.14 Register Map CRC
      15. 8.3.15 Temperature Sensor
        1. 8.3.15.1 Internal Temperature Sensor
        2. 8.3.15.2 External Temperature Sensor
        3. 8.3.15.3 Clock Selection for Temperature Sensor Operation
      16. 8.3.16 General-Purpose Digital Output (GPO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Start-Up Behavior After Power-Up
      3. 8.4.3 Start-Up Behavior After a Pin Reset or RESET Command
      4. 8.4.4 Start-Up Behavior After a Pause in CLKIN
      5. 8.4.5 Synchronization
      6. 8.4.6 Conversion Modes
        1. 8.4.6.1 Continuous-Conversion Mode
        2. 8.4.6.2 Global-Chop Mode
      7. 8.4.7 Power Modes
      8. 8.4.8 Standby Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  Conversion Synchronization or System Reset (SYNC/RESET)
        7. 8.5.1.7  SPI Communication Frames
        8. 8.5.1.8  SPI Communication Words
        9. 8.5.1.9  Short SPI Frames
        10. 8.5.1.10 Communication Cyclic Redundancy Check (CRC)
        11. 8.5.1.11 SPI Timeout
      2. 8.5.2 ADC Conversion Data
      3. 8.5.3 Commands
        1. 8.5.3.1 NULL (0000 0000 0000 0000)
        2. 8.5.3.2 RESET (0000 0000 0001 0001)
        3. 8.5.3.3 STANDBY (0000 0000 0010 0010)
        4. 8.5.3.4 WAKEUP (0000 0000 0011 0011)
        5. 8.5.3.5 LOCK (0000 0101 0101 0101)
        6. 8.5.3.6 UNLOCK (0000 0110 0101 0101)
        7. 8.5.3.7 RREG (101a aaaa annn nnnn)
          1. 8.5.3.7.1 Reading a Single Register
          2. 8.5.3.7.2 Reading Multiple Registers
        8. 8.5.3.8 WREG (011a aaaa annn nnnn)
      4. 8.5.4 ADC Output Buffer and FIFO Buffer
      5. 8.5.5 Collecting Data for the First Time or After a Pause in Data Collection
    6. 8.6 AMC131M03-Q1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Antialiasing
      3. 9.1.3 Minimum Interface Connections
      4. 9.1.4 Multiple Device Configuration
      5. 9.1.5 Calibration
      6. 9.1.6 Troubleshooting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Noise Measurements

Adjust the data rate and gain to optimize the AMC131M03-Q1 noise performance. When averaging is increased by reducing the data rate, noise drops correspondingly. Table 7-1 summarizes the AMC131M03-Q1 noise performance using the 1.2-V internal reference and a 3.3-V power supply at the DVDD pin. Data are representative of typical noise performance at TA = 25°C when fCLKIN = 8.192 MHz. The clock divider is configured to the default setting (that is, the CLK_SEL[1:0] bits in the CLOCK register are set to 00b), thus the modulator clock frequency (fMOD) is equal to fCLKIN / 2. The data shown are typical input-referred noise results with the analog inputs shorted together and taking an average of multiple readings on channel 0. A minimum 1 second of consecutive readings are used to calculate the RMS noise for each reading. Table 7-2 lists the dynamic range, and Table 7-3 lists the effective resolution calculated from the noise data. Equation 1 calculates dynamic range. Equation 2 calculates effective resolution. In each case, VREF corresponds to the internal 1.2-V reference. In global-chop mode, noise improves by a factor of √2.

Noise performance scales with the OSR and gain settings, but is independent from the configured power mode. Thus, the device exhibits the same noise performance in different power modes when selecting the same OSR and gain settings. However, the data rate at the OSR settings scales based on the applied clock frequency for the different power modes.

Equation 1. GUID-5F919C6C-910A-461E-A4B8-F3307E31DF57-low.gif
Equation 2. GUID-616B3C3D-E080-4631-8BBF-7989C9FBF52E-low.gif
Table 7-1 Noise (µVRMS) at TA = 25°C, Channel 0
OSR DATA RATE (kSPS),
fCLKIN = 8.192 MHz		 GAIN
1 2 4 8 16 32 64 128
16384 0.25 3.92 2.15 1.69 0.97 0.84 0.47 0.57 0.51
8192 0.5 4.55 3.16 2.91 2.23 1.67 1.55 1.07 0.92
4096 1 6.35 3.85 3.17 2.43 1.76 1.56 1.53 1.67
2048 2 7.55 4.92 3.92 2.94 2.46 1.68 1.56 1.85
1024 4 8.43 6.06 5.04 4.03 3.39 1.75 2.03 2.86
512 8 12.26 9.21 7.60 6.34 5.15 4.22 4.63 4.36
256 16 17.45 11.88 10.51 8.39 7.10 6.35 5.58 4.75
128 32 26.24 17.20 14.68 10.44 7.75 7.72 8.35 7.87
64 64 77.32 42.11 28.44 16.83 10.89 9.94 9.06 8.99
Table 7-2 Dynamic Range (dB) at TA = 25°C, Channel 0
OSR DATA RATE (kSPS),
fCLKIN = 8.192 MHz		 GAIN
1 2 4 8 16 32 64 128
16384 0.25 107 106 102 101 96 95 87 82
8192 0.5 105 103 97 94 90 85 82 77
4096 1 103 101 97 93 90 85 79 72
2048 2 101 99 95 91 87 84 79 71
1024 4 100 97 92 88 84 84 76 67
512 8 97 93 89 84 80 76 69 64
256 16 94 91 86 82 77 72 68 63
128 32 90 88 83 80 77 71 64 59
64 64 81 80 77 76 74 69 63 57
Table 7-3 Effective Resolution (Bits) at TA = 25°C, Channel 0
OSR DATA RATE (kSPS),
fCLKIN = 8.192 MHz		 GAIN
1 2 4 8 16 32 64 128
16384 0.25 19.2 19.1 18.4 18.2 17.4 17.3 16.0 15.2
8192 0.5 19.0 18.5 17.7 17.0 16.5 15.6 15.1 14.3
4096 1 18.5 18.2 17.5 16.9 16.4 15.5 14.6 13.5
2048 2 18.3 17.9 17.2 16.6 15.9 15.4 14.6 13.3
1024 4 18.1 17.6 16.9 16.2 15.4 15.4 14.2 12.7
512 8 17.6 17.0 16.3 15.5 14.8 14.1 13.0 12.1
256 16 17.1 16.6 15.8 15.1 14.4 13.5 12.7 11.9
128 32 16.5 16.1 15.3 14.8 14.2 13.2 12.1 11.2
64 64 14.9 14.8 14.4 14.1 13.7 12.9 12.0 11.0