SBAS994B September 2023 – September 2023 AMC131M03
PRODUCTION DATA
A pause in the clock signal provided at the CLKIN pin causes the power supply generated by the DC/DC converter on the secondary (high) side to drop and can prevent the ADC circuit on the secondary side from operating. The DC/DC converter is automatically re-enabled when the clock at the CLKIN pin resumes, and the AMC131M03 registers do not need to be reconfigured. However, the supply voltage on the secondary (high) side is not stable until the SEC_FAIL bit in the STATUS register is set to 0b.
Follow the same sequence for reading the SEC_FAIL bit in the STATUS register as described in the Start-Up Behavior After Power-Up section to receive valid conversion data after the clock has been paused and re-started at the CLKIN pin.