SBASAJ7A June   2022  – August 2022

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information 
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications 
    7. 6.7  Safety-Related Certifications 
    8. 6.8  Safety Limiting Values 
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics 
    11. 6.11 Timing Diagrams
    12. 6.12 Insulation Characteristics Curves
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Reference Input
      3. 7.3.3 Isolation Channel Signal Transmission
      4. 7.3.4 Open-Drain Digital Output
        1. 7.3.4.1 Transparent Output Mode
        2. 7.3.4.2 Latch Output Mode
      5. 7.3.5 Power-Up and Power-Down Behavior
      6. 7.3.6 VDD1 Brownout and Power-Loss Behavior
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 DC Link Overcurrent Detection
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
    3. 8.3 Application Curves
    4. 8.4 Best Design Practices
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.2 Detailed Design Procedure

The value of the shunt resistors (R10 and R20) is this example is 10 mΩ. At the desired 30-A overcurrent detection level, the voltage drop across the shunt resistor is 10 mΩ × 30 A = 300 mV. The positive-going trip threshold of the comparator is VREF + VHYS, where VHYS is 4 mV (as specified in the Electrical Characteristics table) and VREF is the voltage across R11 (R12, respectively) that is connected between the REF and GND1 pins. R11 and R12 are calculated as (VTRIP – VHYS) / IREF = (300 mV – 4 mV) / 100 μA = 2.96 kΩ. The next lower value from the E96 series (1% accuracy) is 2.94 kΩ, resulting in an overcurrent trip threshold (rising) of 29.8 A.

A 10-Ω, 1-nF RC filter (R15, C16 and R25, C26, respectively) is placed at the input of the comparator to filter the input signal and reduce noise sensitivity. This filter adds 10 Ω × 1 nF = 10 ns of propagation delay that must be considered when calculating the overall response time of the protection circuit. Larger filter constants are preferable to increase noise immunity if the system can tolerate the additional delay.

Table 8-2 summarizes the key parameters of the design.

Table 8-2 Overcurrent Detection Design Example
PARAMETER VALUE
Reference resistor value (R11, R21) 2.94 kΩ
Reference capacitor value (C15, C25) 100 nF
Reference voltage 296 mV
Reference voltage settling time (to 90% of final value) 690 μs
Overcurrent trip threshold (rising) 298 mV / 29.8 A
Overcurrent trip threshold (falling) 294 mV / 29.4 A