SBASB00 August   2024 AMC3306M25-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications 
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagrams
    12. 5.12 Insulation Characteristics Curves
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Input
      2. 6.3.2 Modulator
      3. 6.3.3 Isolation Channel Signal Transmission
      4. 6.3.4 Digital Output
        1. 6.3.4.1 Output Behavior in Case of a Full-Scale Input
        2. 6.3.4.2 Output Behavior in Case of a High-Side Supply Failure
      5. 6.3.5 Isolated DC/DC Converter
      6. 6.3.6 Diagnostic Output
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Digital Filter Usage
    2. 7.2 Typical Application
      1. 7.2.1 Onboard Charger (OBC) Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Shunt Resistor Sizing
          2. 7.2.1.2.2 Input Filter Design
          3. 7.2.1.2.3 Bitstream Filtering
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Best Design Practices
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Insulation Specifications

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance(1) Shortest pin-to-pin distance through air ≥ 8 mm
CPG External creepage(1) Shortest pin-to-pin distance across the package surface ≥ 8 mm
DTI Distance through insulation Minimum internal gap (internal clearance - capacitive signal isolation) ≥ 21 µm
DTI Distance through insulation Minimum internal gap (internal clearance - transformer power isolation) ≥ 120 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 ≥ 600 V
Material group According to IEC 60664-1 I
Overvoltage category
per IEC 60664-1		 Rated mains voltage ≤ 600VRMS I-III
Rated mains voltage ≤ 1000VRMS I-II
DIN EN IEC 60747-17 (VDE 0884-17)
VIORM Maximum repetitive peak isolation voltage At AC voltage 1700 VPK
VIOWM Maximum-rated isolation
working voltage		 At AC voltage (sine wave) 1200 VRMS
At DC voltage 1700 VDC
VIOTM Maximum transient
isolation voltage		 VTEST = VIOTM, t = 60s (qualification test),
VTEST = 1.2 × VIOTM, t = 1s (100% production test)		 6000 VPK
VIMP Maximum impulse voltage(2) Tested in air, 1.2/50µs waveform per IEC 62368-1 7700 VPK
VIOSM Maximum surge
isolation voltage(3)		 Tested in oil (qualification test),
1.2/50µs waveform per IEC 62368-1		 10000 VPK
qpd Apparent charge(4) Method a, after input/output safety test subgroups 2 and 3,
Vpd(ini) = VIOTM, tini = 60s, Vpd(m) = 1.2 × VIORM, tm = 10s		 ≤ 5 pC
Method a, after environmental tests subgroup 1,
Vpd(ini) = VIOTM, tini = 60s, Vpd(m) = 1.6 × VIORM, tm = 10 s		 ≤ 5
Method b1, at preconditioning (type test) and routine test,
Vpd(ini) = 1.2 x VIOTM, tini = 1s, Vpd(m) = 1.875 × VIORM, tm = 1s		 ≤ 5
Method b2, at routine test (100% production)(6),
Vpd(ini) = Vpd(m) = 1.2 x VIOTM, tini =  tm = 1s		 ≤ 5
CIO Barrier capacitance,
input to output(5)		 VIO = 0.5 VPP at 1MHz ~4.5 pF
RIO Insulation resistance,
input to output(5)		 VIO = 500 V at TA = 25°C > 1012 Ω
VIO = 500 V at 100°C ≤ TA ≤ 125°C > 1011
VIO = 500 V at TS = 150°C > 109
Pollution degree 2
Climatic category 40/125/21
UL1577
VISO Withstand isolation voltage VTEST = VISO, t = 60s (qualification test),
VTEST = 1.2 × VISO, t = 1s (100% production test)		 4250 VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application.Maintain the creepage and clearance distance of a board design to make sure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.
(2) Testing is carried out in air to determine the surge immunity of the package.
(3) Testing is carried in oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier are tied together, creating a two-pin device.
(6) Either method b1 or b2 is used in production.