SBASAQ5 Data sheet

SBASAQ5A june 2023 – august 2023 AMC3311

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

DWE|16
- MPSS091

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6.13 Typical Characteristics

at VDD = 3.3 V, IN = 0 V to 2 V, and f_IN = 10 kHz (unless otherwise noted)

Figure 6-5 Output Voltage vs Input Voltage

Figure 6-7 Input Bias Current vs Supply Voltage

Figure 6-9 Input Capacitance vs Input Signal Frequency

Figure 6-11 Output Common-Mode Voltage vs Temperature

Figure 6-13 Output Phase vs Input Frequency

Figure 6-15 Output Bandwidth vs Temperature

Figure 6-17 Offset Error vs Temperature

Figure 6-19 Gain Error vs Temperature

Figure 6-21 Nonlinearity vs Supply Voltage

Figure 6-23 Signal to Noise Ratio vs Input Voltage

V_IN = 2 V

Figure 6-25 Signal-to-Noise Ratio vs Temperature

Figure 6-27 Total Harmonic Distortion vs Temperature

Figure 6-29 Power-Supply Rejection Ratio vs Ripple Frequency

Figure 6-31 Input Supply Current vs Supply Voltage

Figure 6-33 High-Side LDO Line Regulation

Figure 6-35 Output Rise and Fall Time vs Supply Voltage

Figure 6-37 V_IN to V_OUT Signal Delay Time vs Supply Voltage

Total uncalibrated output error is defined as:
(V_OUT – V_IN × G) / (V_Clipping × G), where G is the nominal gain of the device (1 V/V) and V_Clipping is 2.516 V

Figure 6-6 Total Uncalibrated Output Error vs Input Voltage

Figure 6-8 Input Bias Current vs Temperature

Figure 6-10 Output Common-Mode Voltage vs Supply Voltage

Figure 6-12 Normalized Gain vs Input Frequency

Figure 6-14 Output Bandwidth vs Supply Voltage

Figure 6-16 Offset Error vs Supply Voltage

Figure 6-18 Gain Error vs Supply Voltage

Figure 6-20 Nonlinearity vs Input Voltage

Figure 6-22 Nonlinearity vs Temperature

V_IN = 2 V

Figure 6-24 Signal-to-Noise Ratio vs Supply Voltage

Figure 6-26 Total Harmonic Distortion vs Supply Voltage

Figure 6-28 Input-Referred Noise Density vs Frequency

Figure 6-30 Power-Supply Rejection Ratio vs Temperature

Figure 6-32 Input Supply Current vs Temperature

Figure 6-34 High-Side LDO Load Regulation

Figure 6-36 Output Rise and Fall Time vs Temperature

Figure 6-38 V_IN to V_OUT Signal Delay Time vs Temperature