SBAS475A June   2009  – January 2023 AMC6821-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1 ADC Converter
      2. 8.2.2 Temperature Sensor
        1. 8.2.2.1 Series Resistance Cancellation
        2. 8.2.2.2 Reading Temperature Data
        3. 8.2.2.3 Temperature Out-of-Range Detection
        4. 8.2.2.4 Remote Temperature Sensor Failure Detection
      3. 8.2.3 PWM Output
      4. 8.2.4 PWM Waveform Setting
      5. 8.2.5 Fan Speed Measurement
        1. 8.2.5.1 Tach-Data Register
          1. 8.2.5.1.1 Reading the Tach Data Register
          2. 8.2.5.1.2 RPM Measurement Rate
          3. 8.2.5.1.3 Select Number of Pulses/Revolution
          4. 8.2.5.1.4 Tach Mode Selection
          5. 8.2.5.1.5 Fan RPM Out-of-Range Detection
      6. 8.2.6 Fan Failure Detection
      7. 8.2.7 FAN-FAULT Pin
      8. 8.2.8 Fan Control
        1. 8.2.8.1 THERM Pin and External Hardware Control
          1. 8.2.8.1.1 THERM Pin as an Output
          2. 8.2.8.1.2 THERM Pin as an Input
        2. 8.2.8.2 Fan Spin-Up
        3. 8.2.8.3 Normal Fan Speed Control
          1. 8.2.8.3.1 Software DCY Control Mode
          2. 8.2.8.3.2 Software-RPM Control Mode (Fan Speed Regulator)
          3. 8.2.8.3.3 Auto Temperature Fan Mode
      9. 8.2.9 Interrupt
        1. 8.2.9.1 OVR Pin
        2. 8.2.9.2 SMBALERT Pin
        3. 8.2.9.3 SMBALERT Interrupt Behavior
        4. 8.2.9.4 Handling SMBALERT Interrupts
    3. 8.3 Device Functional Modes
    4. 8.4 Programming
      1. 8.4.1 SMBus Interface
        1. 8.4.1.1 Communication Protocols
      2. 8.4.2 SMBus Alert Response Address (ARA)
      3. 8.4.3 Power-On Reset and Start Operation
    5. 8.5 Register Map
      1. 8.5.1 Register Description
        1. 8.5.1.1 Device Configuration Registers
        2. 8.5.1.2 Device Status Registers
        3. 8.5.1.3 Fan Controller Registers
        4. 8.5.1.4 Temperature Data Registers
        5. 8.5.1.5 Temperature Limit Registers
          1. 8.5.1.5.1 Tach-Data Register
          2. 8.5.1.5.2 Tach Setting Register
          3. 8.5.1.5.3 Tach Low Limit Register
          4. 8.5.1.5.4 Tach High Limit Register
  9. 9 Application and Implementation
    1. 9.1 Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.1 SMBus Interface

The AMC6821-Q1 communicates through the serial system management bus (SMBus). The AMC6821-Q1 is connected to this bus as a slave device, under the control of a bus master. The AMC6821-Q1 has a 7-bit serial bus address that is programmable by properly connecting the address pins A0 and A1. Table 8-4 shows the selection of the AMC6821-Q1 slave address. The address selection pins should be either tied directly to VDD or GND. For the NC condition, they should be unconnected with minimum trace capacitance. Note that the address is checked only on a reset or power-up condition.

Table 8-4 AMC6821-Q1 Address Select(1)
A0A1ADDRESS
GNDGND0011000
NCGND0011010
VDDGND0011001
GNDNC0101100
NCNC0101110
VDDNC0101101
GNDVDD1001100
NCVDD1001110
VDDVDD1001101
(1) NC = No connection.