8.3.1.1 DAC Output Range and Clamp Configuration

The twelve DACs are split into four total groups: two groups of two DACs (DAC groups B and C) and two groups of four DACs (DAC groups A and D). All of the DACs in a given group share the same output range and clamp voltage value however these settings can be set independently for each DAC group. After power-on or a reset event, the DAC output are directed automatically to their corresponding clamp value and all DAC buffer and active registers are set to their default values.

The output range for each DAC group is configured as either positive or negative through its corresponding VRANGE terminal. The VRANGE terminals can be driven directly by the REF_OUT1 and REF_OUT2 +2.5-V outputs. When a DAC group is in positive output range the DAC Range register (address 0x1E) can be set to specify an output range of 0 to +5-V instead of the default range of 0 to +10-V.

Additionally the power-on-reset and clamp voltage value of each DAC group is set by its corresponding AVSS terminal. It is imperative that the clamp voltage setting for a DAC group matches its operating voltage range. The recommended connections for AVSS are: AGND for the positive output ranges, in which case the clamp voltage is 0-V; and -12-V for the negative output range, in which case the clamp voltage is AVSS + 2-V.

The full-scale output range for each DAC group is limited by the power supplies AVCC and its corresponding AVSS. The maximum and minimum outputs cannot exceed AVCC or be lower than AVSS, respectively.

8.3.1.2 DAC Register Structure

The DACs input data is written to the individual DAC Data registers (address 0x50 – 0x67) in straight binary format for all output ranges.

Data written to the DAC Data registers is initially stored in the DAC buffer registers. Transfer of data from the DAC buffer registers to the active registers is initiated by an update command in the Register Update register (address 0x0F). Once the active registers are updated, the DAC outputs change to their new values.

The host has the option to read from either the buffer registers or the active registers when accessing the DAC Data registers. The DAC read back option is configured by the READBACK bit in the Interface Configuration 1 register (address 0x01).

8.3.1.3 DAC Clear Operation

Each DAC can be set to a clear state using either hardware or software. When a DAC goes to clear state it is loaded with a zero-code input and the output voltage is set according to the operating output range. The DAC buffer or active registers do not change when the DACs enter the clear state thus allowing the possibility to return to the same voltage being output before the clear event was issued. Note that the DAC Data registers can be updated while the DACs are in clear state allowing the DACs to output new values upon return to normal operation. When the DACs exit the clear state they are immediately loaded with the data in the DAC active registers and the output is set back to the corresponding level to restore operation.

The DAC Clear registers (address 0xB0 – 0xB1) enable independent control of each DAC clear state through software. The DACs can also be forced to a clear state through hardware using the ALARMIN terminal. For a detailed description of this method please refer to the Programmable Out-of-Range Alarms section.

The ALARMIN controlled clear mechanism is a special case of the device capability to force the DACs into clear state as a response to an alarm event. To enable this functionality the clear-state controlling alarm events must first be enabled as DAC clear alarm sources in the DAC Clear Source registers (address 0x1A – 0x1B). Additionally the DAC outputs to be cleared by the selected alarm events need also to be specified in the DAC Clear Enable registers (address 0x18 – 0x19).

When an alarm event is triggered, the corresponding alarm bit in the Alarm Status registers is set and all the DACs set to clear in response to this alarm in the DAC Clear Enable registers enter a clear state. Once the alarm bit is cleared, and as long as no other clear-state controlling alarm events have been triggered, the DACs get re-loaded with the contents of the DAC active registers and the outputs update accordingly.

Figure 42. Simplified AMC7832 DAC Block Diagram

8.3.2.1 Analog Inputs

The AMC7832 has 17 uncommitted analog inputs for external voltage sensing. Twelve of these inputs (ADC_0 to ADC_11) are bipolar and the other five (LV_ADC12 to LV_ADC16) unipolar. Figure 43 shows the equivalent circuit for the external analog input terminals. All switches are open while the ADC is in idle state.

Figure 43. ADC External Inputs Equivalent Circuit

In order to achieve specified performance, especially at higher input frequencies, it is recommended to drive each analog input terminal with a low impedance source. An external amplifier can also be used to drive the input terminals.

8.3.2.1.1 Bipolar Analog Inputs

The AMC7832 supports up to twelve bipolar analog inputs. The analog input range for these channels is -12.5-V to +12.5-V. The bipolar signal is scaled internally through a resistor divider so that it maps to the native input range of the ADC (0-V to 2 × VREF). The input resistance of the scaling network is 175-kΩ.

The bipolar analog input conversion values are stored in straight binary format in the ADC-Data registers (address 0x20 – 0x37). The LSB size for these channels is 10 × VREF/4096. With the internal reference equal to 2.5-V the voltage value is given by,

Equation 1.

A typical application for the bipolar channels is monitoring of the twelve DAC outputs in the device. In this application the bipolar inputs can be driven directly. However in applications where the signal source has high impedance, it is recommended that the analog input is buffered prior to be input to the AMC7832. When driven from a low impedance source such as the AMC7832 DAC outputs, the network is designed to settle well before the start of conversion. Additional impedance may affect the settling and divider accuracy of this network.

8.3.2.1.2 Unipolar Analog Inputs

In addition to the bipolar input channels, the AMC7832 includes five unipolar analog inputs. The analog input range for these channels is 0-V to 2 × VREF with the LSB size for these channels given by 2 × VREF/4096.

The unipolar analog input conversion values are stored in straight binary format in the ADC-Data registers (address 0x38 – 0x41). With the internal reference equal to 2.5-V the voltage value is given by,

Equation 2.

In applications where the signal source has high impedance, it is recommended that the unipolar analog input is buffereded externally.

8.3.2.2 ADC Sequencing

The AMC7832 ADC supports two conversion methods: direct-mode and auto-mode. The conversion method can be selected in the ADC Configuration register (address 0x10). The default conversion method is direct-mode.

In both methods, the single channel or sequence of channels to be converted by the ADC must be first configured in the ADC MUX Configuration registers (address 0x13 – 0x15). The input channels to the ADC include 12 external bipolar inputs, 5 external unipolar inputs and the internal temperature sensor.

In direct-mode conversion, the selected ADC input channels are converted on demand by issuing an ADC trigger signal. After the last enabled channel is converted, the ADC goes into idle state and waits for a new trigger.

In auto-mode conversion, the selected ADC input channels are converted continuously. The conversion cycle is initiated by issuing an ADC trigger. Upon completion of the first conversion sequence another sequence is automatically started. Conversion of the selected channels is done repeatedly until the auto-mode conversion is stopped by issuing a second trigger signal. To ensure data for all channels is updated correctly in the ADC data registers the auto-mode conversion stop trigger should be synchronized with the data available indicator signal (DAV, terminal 12).

Figure 44. AMC7832 ADC Conversion Sequence

Regardless of the selected conversion method, the following registers should only be updated while the ADC is in idle state:

• ADC Configuration Register (address 0x10)
• False Alarm Configuration Register (address 0x11)
• ADC MUX Configuration Registers (address 0x13 – 0x15)
• Threshold Registers (0x80 – 0x97)
• Hysteresis Register (0xA0 – 0xA5)
• Power Down Registers (0xB2 - 0xB3)

8.3.2.3 ADC Synchronization

A trigger signal is required for getting the ADC in and out of idle state. The ADC trigger can be generated either through software (ICONV bit in the ADC Trigger Register, 0xC0) or hardware (GPIO2/ADCTRIG, terminal 11). In order to use the GPIO2/ADCTRIG terminal as an ADC trigger, the terminal must be configured accordingly in the GPIO Configuration register (address 0x12). When the terminal is configured as a trigger, a falling edge starts the sampling and conversion of the ADC.

The ADC Data registers (0x20 – 0x41) and Temperature Data registers (0x78 – 0x79) should only be accessed while the ADC is in idle state or between conversion sequences if the ADC is in auto-mode. A data available indicator signal is generated by the device to track the ADC status. Failure to satisfy the synchronization requirements could lead to erroneous data reads.

The data available indicator signal is output through the GPIO3/DAV terminal. The GPIO3/DAV terminal must be configured in the GPIO Configuration register (address 0x12) as an interrupt. In addition to the terminal indicator the device provides a data available flag accessible through the serial interface (DAVF bit in the General Status Register, 0x72). The DAV terminal is available in both auto and direct-mode but the DAVF flag is only available in direct mode.

The terminal and flag behavior are dependent on the conversion mode. In direct-mode, after the conversion is completed and the ADC returns to idle state, the DAVF bit is set immediately to ‘1’ and the DAV terminal is active (low) to indicate new data is available. The terminal and flag are cleared automatically once a new conversion is started or one of the ADC Data or Temperature Data registers is accessed. In auto-mode, the DAVF bit is fixed to ‘0’ and therefore synchronization is always done through the DAV terminal. After one auto-mode conversion sequence is complete a 1µs pulse (low) is issued on the DAV terminal. When an auto-mode conversion needs to be stopped it is recommended to do so in synchronization with DAV.

Figure 45. ADC Software Trigger Synchronization

Figure 46. ADC Hardware Trigger Synchronization

8.3.2.4 Programmable Out-of-Range Alarms

The AMC7832 is capable of continuously analyzing the 5 external unipolar inputs and internal temperature sensor conversion results for normal operation.

Normal operation is established through the Lower and Upper Threshold registers (address 0x80 – 0x97). When any of the monitored inputs is out of the specified range, an alarm event is issued and the global alarm bit, GALR in the General Status register (0x72) is set. Details on the source of the alarm event can be determined through the Alarm Status registers (0x70 – 0x71).

The ALARM-LATCH-DIS bit in the ALARMOUT Source 1 register (address 0x1D) sets the latching behavior for all alarms (except for the ALARMIN alarm which is always unlatched). When the ALARM-LATCH-DIS bit is cleared to ‘0’ the alarm bits in the Alarm Status registers are latched. The alarm bits are referred to as being latched because they remain set until read by software. This design ensures that out-of-limit events cannot be missed if the software is polling the device periodically. The alarm bits are cleared when their corresponding Alarm Status register is read, and are reasserted if the out-of limit condition still exists on the next monitoring cycle, unless otherwise noted. When the ALARM-LATCH-DIS bit is set to ‘1’, the alarm bits are not latched. The alarm bits in the Alarm Status registers go to '0' when the error condition subsides, regardless of whether the bit is read or not.

Figure 47. AMC7832 Alarm Status Register

All of the alarms can be set to activate the ALARMOUT terminal. The GPIO1/ALARMOUT terminal must be configured accordingly in the GPIO Configuration register (address 0x12) to enable this functionality. The ALARMOUT terminal works as an interrupt to the host so that it may query the Alarm Status registers to determine the alarm source. Any alarm event can activate the terminal as long as the alarm is not masked in the ALARMOUT Source registers (address 0x1C – 0x1D). When an alarm event is masked, the occurrence of the event sets the corresponding status bit in the Alarm Status registers to '1', but does not activate the ALARMOUT terminal.  

8.3.2.4.1 Unipolar Inputs Out-of-Range Alarms

The AMC7832 provides out-of-range detection for the five external unipolar ADC inputs (LV_ADC12 to LV_ADC16, terminals 41 - 45). When the measurement is out-of-range, the corresponding alarm bit in the Alarm Status 0 register (address 0x70) is set to '1' to flag the out-of-range condition. The values in the ADC Upper and Lower Threshold registers (address 0x80 – 0x93) define the upper and lower bound thresholds for all five inputs.

Figure 48. Unipolar Inputs Out-of-Range Alarms

8.3.2.4.2 Internal Temperature Sensor Out-of-Range Alarms

The AMC7832 includes high-limit and low-limit detection for the internal temperature sensor. The values in the LT Upper and Lower Threshold registers (address 0x94 – 0x97) set the limits for the temperature sensor. The temperature sensor detector can issue either a high-alarm (LT-HIGH-ALR bit) or a low-alarm (LT-LOW-ALR bit) in the Alarm Status 1 register (address 0x71) depending on whether the high or low thresholds were exceeded. To implement single, upper-bound threshold detection for the temperature sensor, the host processor can set the upper-bound threshold to the desired value and the lower-bound threshold to the default value. For lower-bound threshold detection, the host processor can set the lower-bound threshold to the desired value and the upper-bound threshold to the default value.

In addition to the programmable threshold alarms the temperature sensor detection circuit also includes a die thermal alarm flag which continuously monitors the die temperature. When the die temperatures exceeds +150˚C the die thermal alarm flag (THERM-ALR bit) in the Alarm Status 1 register (address 0x71) is set. The internal temperature sensor must be enabled for this alarm to be functional.

Figure 49. Internal Temperature Out-of-Range Alarms

8.3.2.4.4 Hysteresis

If a monitored signal is out of range and the alarm is enabled, the corresponding alarm bit is set ('1'). However, the alarm condition is cleared only when the conversion result returns to a value of at least HYST below the value of the high threshold register, or HYST above the value of the low threshold register. The ADC and LT Hysteresis registers (address 0xA0 – 0xA4) store the hys value for the external unipolar inputs and internal temperature sensor programmable alarms. HYST is the programmable value of hysteresis: 0 LSB to 127 LSB for the unipolar inputs alarms, and 0°C to +31°C for the internal temperature sensor alarms. The die thermal alarm hysteresis is fixed at 8°C.

Figure 50. AMC7832 Hysteresis

Table 3. Temperature Sensor Data Format

Table 4. Dual Functionality GPIO Pins

Table 6. Register name: Interface Configuration 0 – Address: 0x00, Default: 0x3C (READ/WRITE)

Table 7. Register name: Interface Configuration 1 – Address: 0x01, Default: 0x00 (READ/WRITE)

Table 8. Register name: Device Configuration – Address: 0x02, Default: 0x03 (READ/WRITE)

Table 9. Register name: Chip Type – Address: 0x03, Default: 0x08 (READ ONLY)

Table 10. Register name: Chip ID low byte – Address: 0x04, Default: 0x32 (READ ONLY)

Table 11. Register name: Chip ID high byte – Address: 0x05, Default: 0x0C (READ ONLY)

Table 12. Register name: Version ID – Address: 0x06, Default: 0x00 (READ ONLY)

Table 13. Register name: Manufacturer ID low byte – Address: 0x0C, Default: 0x51 (READ ONLY)

Table 14. Register name: Manufacturer ID high byte – Address: 0x0D, Default: 0x04 (READ ONLY)

Table 15. Register name: Register Update – Address: 0x0F, Default: 0x00 (SELF CLEARING)

Table 16. Register name: ADC Configuration – Address: 0x10, Default: 0x00 (READ/WRITE)

Table 17. Register name: False Alarm Configuration – Address: 0x11, Default: 0x70 (READ/WRITE)

Table 18. Register name: GPIO Configuration – Address: 0x12, Default: 0x00 (READ/WRITE)

Table 19. Register name: ADC MUX Configuration 0 – Address: 0x13, Default: 0x00 (READ/WRITE)

Table 20. Register name: ADC MUX Configuration 1 – Address: 0x14, Default: 0x00 (READ/WRITE)

Table 21. Register name: ADC MUX Configuration 2 – Address: 0x15, Default: 0x00 (READ/WRITE)

Table 22. Register name: DAC Clear Enable 0 – Address: 0x18, Default: 0x00 (READ/WRITE)

Table 23. Register name: DAC Clear Enable 1 – Address: 0x19, Default: 0x00 (READ/WRITE)

Table 24. Register name: Register name: DAC Clear Source 0 – Address: 0x1A, Default: 0x00 (READ/WRITE)

Table 25. Register name: Register name: DAC Clear Source 1 – Address: 0x1B, Default: 0x00 (READ/WRITE)

Table 26. Register name: ALARMOUT Source 0 – Address: 0x1C, Default: 0x00 (READ/WRITE)

Table 27. Register name: ALARMOUT Source 1 – Address: 0x1D, Default: 0x00 (READ/WRITE)

Table 28. Register name: DAC Range – Address: 0x1E, Default: 0x00 (READ/WRITE)

Table 29. Register name: ADCn-Data (low byte) – Address: 0x20 - 0x41, Default: 0x00 (READ ONLY)

Table 30. Register name: ADCn-Data (high byte) – Address: 0x20 - 0x41, Default: 0x00 (READ ONLY)

Table 31. Register name: DACn-Data (low byte) – Address: 0x50 - 0x67, Default: 0x00 (READ/WRITE)

Table 32. Register name: DACn-Data (high byte) – Address: 0x50 - 0x67, Default: 0x00 (READ/WRITE)

Table 33. Register name: Register name: Alarm Status 0 – Address: 0x70, Default: 0x00 (READ ONLY)

Table 34. Register name: Alarm Status 1 – Address: 0x71, Default: 0x00 (READ ONLY)

Table 35. Register name: General Status – Address: 0x72, Default: 0x00 (READ ONLY)

Table 36. Register name: Temperature Data (low byte) – Address: 0x78, Default: 0x00 (READ ONLY)

Table 37. Register name: Temperature Data (high byte) – Address: 0x79, Default: 0x00 (READ ONLY)

Table 38. Register name: GPIO – Address: 0x7A, Default: 0xFF (READ/WRITE)

Table 39. Register name: ADCn-Upper-Thresh (low byte) – Address: 0x80 - 0x93, Default: 0xFF (READ/WRITE)

Table 40. Register name: ADCn-Upper-Thresh (high byte) – Address: 0x80 - 0x93, Default: 0x0F (READ/WRITE)

Table 41. Register name: ADCn-Lower-Thresh (low byte) – Address: 0x80 - 0x93, Default: 0x00 (READ/WRITE)

Table 42. Register name: ADCn-Lower-Thresh (high byte) – Address: 0x80 - 0x93, Default: 0x00 (READ/WRITE)

Table 43. Register name: LT-Upper-Thresh (low byte) – Address: 0x94, Default: 0xFF (READ/WRITE)

Table 44. Register name: LT-Upper-Thresh (high byte) – Address: 0x95, Default: 0x07 (READ/WRITE)

Table 45. Register name: LT-Lower-Thresh (low byte) – Address: 0x96, Default: 0x00 (READ/WRITE)

Table 46. Register name: LT-Lower-Thresh (high byte) – Address: 0x97, Default: 0x08 (READ/WRITE)

Table 47. Register name: ADCn-Hysteresis – Address: 0xA0 - 0xA4, Default: 0x08 (READ/WRITE)

Table 48. Register name: LT-Hysteresis – Address: 0xA5, Default: 0x08 (READ/WRITE)

Table 49. Register name: DAC Clear 0 – Address: 0xB0, Default: 0x00 (READ/WRITE)

Table 50. Register name: DAC Clear 1 – Address: 0xB1, Default: 0x00 (READ/WRITE)

Table 51. Register name: Register name: Power-down 0 – Address: 0xB2, Default: 0x00 (READ/WRITE)

Table 52. Register name: Register name: Power-down 1 – Address: 0xB3, Default: 0x00 (READ/WRITE)

Table 53. Register name: ADC Trigger – Address: 0xC0, Default: 0x00 (WRITE ONLY)