7.3.1.1 DAC Configuration

The eight DACs are split into bipolar and auxiliary outputs based on their output range and clamping capabilities as listed in Table 1. After power-on or a reset event the DAC outputs are directed automatically to the corresponding clamp value and all DAC buffer and active registers are set to the default values.

7.3.1.1.1 Bipolar DACs (DAC1, DAC2, DAC3, and DAC4)

The bipolar DACs are configured as DAC pairs (DAC1-DAC2 and DAC3-DAC4). The output range for each bipolar DAC pair can be configured through the DAC Range register (address 0x16) to one of the following: 0 to 5 V, –5 to 0 V, or –4 to 1 V. The POR and clamp value of each DAC pair is set by the pins VCLAMP1 (for the DAC1-DAC2 pair) and VCLAMP2 (for the DAC3-DAC4 pair) to any voltage between AV_SS and 0 V during normal operation. If AV_DD falls outside the device specified operating range the bipolar DACs enter the special AV_SS clamp mode and their outputs are set to AV_SS. The full-scale output range of the bipolar DACs is limited by the power supplies, AV_DD and AV_SS.

The bipolar DACs operate as standalone DACs when the AMC7834 is set in open-loop mode (LOOP-EN bit set to 0 in register 0x10). Figure 45 shows a high level block diagram of each bipolar DAC when operating in open-loop mode.

Figure 45. Bipolar DAC Block Diagram — Open Loop Operation

Alternatively, with the AMC7834 set in closed-loop mode (LOOP-EN bit set to 1 in register 0x10) each bipolar DAC output updates automatically in response to one of the four current sensors in the device (see the Closed-Loop Mode section). In closed-loop mode the AMC7834 bipolar DACs operate as four autonomous closed-loop current controllers.

The DAC upper threshold registers (address 0x4E through 0x4F) sets an upper output limit other than full-scale for the bipolar DACs when operating in closed-loop mode. The upper threshold feature can be used to limit the maximum output voltage for each bipolar DAC. When a closed-loop controller attempts to set its bipolar DAC to a value exceeding the corresponding DAC upper threshold register, the DAC is updated with the threshold code instead.

7.3.1.1.2 Auxiliary DACs (AUXDAC1, AUXDAC2, AUXDAC3, and AUXDAC4)

The output range for each auxiliary DAC can be independently set through the DAC Range register (address 0x16) to either 0 to 5 V or 2.5 to 7.5 V. The POR and clamp value of each of the auxiliary DACs is fixed to AGND. The maximum and minimum outputs from these DACs cannot exceed AV_CC or be lower than AGND, respectively. Figure 46 shows a high level block diagram of each auxiliary DAC.

Figure 46. Auxiliary DAC Block Diagram

7.3.1.2 DAC Register Structure

The input data of the DACs is written to the individual DAC data registers (address 0x30 through 0x37) in straight binary format for all output ranges (see Table 2).

Data written to the DAC data registers is initially stored in the DAC buffer registers. The transfer of data from the DAC buffer registers to the active registers can be set to occur immediately (asynchronous mode) or initiated by a DAC trigger signal (synchronous mode). When the active registers are updated, the DAC outputs change to the new values. When the host reads from a DAC data register, the value held in the DAC active register is returned (not the value held in the buffer register).

The update mode of the DACs is determined by the DAC sync register (address 0x15). In asynchronous mode, a write to a DAC data register results in an immediate update of the DAC active register and the corresponding output. In synchronous mode, writing to a DAC data register does not automatically update the DAC output. Instead, the update occurs only after a DAC trigger event. A DAC trigger is generated either through the DAC-TRIG bit in the DAC and ADC trigger register (address 0x1C) or by the DACTRIG pin. By setting the synchronization properly, several DACs can be updated simultaneously.

7.3.1.3 DAC Clamp Operation

Each DAC can be set to a clamp mode using either hardware or software. When a DAC goes to clamp mode, the DAC output is immediately set to the corresponding clamp voltage. However, clamping does not clear the DAC buffer or active registers making it possible to return to the same voltage being output before the clamp event was issued. The DAC data registers can be updated while the DACs are in clamp mode allowing the DACs to output new values upon return to normal operation. When the DACs exit clamp mode, the DACs are immediately loaded with the data in the DAC active registers and the output is set back to the corresponding level to restore operation regardless of the DAC synchronization setting.

The clamp voltage is dependent on the DAC output:

• DAC1 and DAC2: Clamp voltage is set by the voltage at pin VCLAMP1 and is equal to –3 × VCLAMP1 during normal operation. In the special AV_SS clamp mode the clamp voltage for DAC1 and DAC2 is fixed to AV_SS.
• DAC3 and DAC4: Clamp voltage is set by the voltage at pin VCLAMP2 and is equal to –3 × VCLAMP2 during normal operation. In the special AV_SS clamp mode the clamp voltage for DAC3 and DAC4 is fixed to AV_SS.
• AUXDAC1 through AUXDAC4: The clamp voltage for each of the auxiliary DACs is fixed to AGND.

The clamp register (address 0x17) allows clamping of the DACs through software. The DAC1-DAC2 pair, DAC3-DAC4 pair, and each auxiliary DAC has a corresponding DAC clamp bit. Setting this bit to 1 forces the corresponding DAC pair or individual auxiliary DAC to enter clamp mode. Clearing the bit to 0 restores normal operation.

Additionally, in the unique case of the AV_DD supply falling outside its specified operating range the bipolar DACs enter the alternative AV_SS clamp mode. With the AV_DD supply outside of the valid operating range the bipolar DAC output buffers become inactive thus creating the potential for unexpected output voltages. The AV_SS clamp mode prevents this condition by setting all bipolar DAC outputs to AV_SS through a resistive path.

The DACs can also be forced to clamp through the SLEEP1 and SLEEP2 pins. When either pin goes high, the corresponding DAC pair and auxiliary DAC associated with each pin are forced into clamp mode. The SLEEP1 register (address 0x18) determines which DACs are forced to clamp when the SLEEP1 pin goes high. The register contains one bit for each DAC pair (DAC1-DAC2 and DAC3-DAC4) and each auxiliary DAC. Likewise, the SLEEP2 register (address 0x19) determines which DACs go into clamp when the SLEEP2 pin goes high. In addition to forcing the DACs into clamp mode, the SLEEP1 and SLEEP2 pin and registers allow control of the PA_ON pin.

Although a high state on the SLEEP pins force the associated DACs to clamp immediately, returning to a low state does not necessarily force the DAC to return to normal operation. If the end application requires the DACs to exit clamp mode in a particular sequence, this sequence can be controlled by the SNOOZE bits in the SLEEP1 and SLEEP2 registers. When a SNOOZE bit is set to 1, bringing a DAC back to normal operation requires the SLEEP pin to return to a low state first, followed by a write to the DAC clamp register (address 0x17) to clear the clamp condition. If the SNOOZE bit is cleared to 0, setting the SLEEP pin to a low state immediately clears the clamp condition and returns the DAC to normal operation without the need for any register writes.

The DACs can be forced to enter clamp mode by the alarm events controlling the ALARMOUT pin. The ALARMOUT clamp register (address 0x1A) selects the DAC or DAC pairs that enter clamp mode when the ALARMOUT pin goes active. Restoring the ALARMOUT pin does not automatically return the DAC or DAC pairs back to normal operation.

7.3.2.1 External Analog Inputs

The AMC7834 has 4 analog inputs for external voltage sensing (ADC1 through ADC4). Figure 47 shows the equivalent circuit for each external analog input pin. The two diodes, D1 and D2, provide electrostatic discharge (ESD) protection for the individual analog pins. Diode D1 turns on when any of the inputs is greater than AV_DD + 0.3 V. Similarly diode D2 turns on when any of the inputs is less than AGND – 0.3 V. The switch is open while the ADC is in the READY state.

Figure 47. ADC External Inputs Equivalent Circuit

The analog input range for inputs ADC1 through ADC4 is 0 V to V_ref and the LSB (least-significant bit) size is given by V_ref / 4096. The analog input conversion values are stored in straight binary format in the ADC-External Data registers (address 0x24 through 0x27). The input voltage is calculated using Equation 2.

Equation 2.

To achieve specified performance it is recommended to drive each analog input pin with a low impedance source. In applications where the signal source has high impedance, analog input must be buffered.

7.3.2.2 Internal Bipolar DAC Monitoring Inputs

The AMC7834 has 4 internal inputs used for monitoring the bipolar DAC outputs (ADCINT1 through ADCINT4). The internal monitoring inputs are particularly useful when the AMC7834 operates in closed-loop mode as the bipolar DAC outputs are autonomously updated by the closed-loop controllers. Continuous monitoring of the bipolar DAC outputs helps in detecting closed-loop controller issues.

The input range for the internal monitoring channels is -2 × V_ref to V_ref and the LSB size is given by 3 × V_ref/4096. The monitored signals are scaled through a resistor divider so that they map to the native input range of the ADC (0 to 2 × V_ref).

The internal monitoring inputs conversion values are stored in straight binary format in the ADC-Internal Data registers (address 0x20 through 0x23). The monitored bipolar DAC output voltage is calcualted by Equation 3.

Equation 3.

7.3.2.3 ADC Sequencing

The AMC7834 supports autonomous and direct-mode ADC conversions. The conversion method is selected in the AMC configuration 0 register (address 0x10). The default conversion method is autonomous conversion. In both conversion methods, the channel or group of channels to be converted by the ADC must be first configured in the ADC MUX register (address 0x12). The input channels to the ADC include 4 external inputs, 4 DAC monitoring internal inputs, 4 current-sense inputs, 2 remote temperature sensor inputs, and the internal temperature sensor.

The ADC must be in the READY state before a conversion cycle is started. The ADC enters the READY state once powered-up and at least one input channel is enabled in the ADC MUX register. The ADC READY status can be determined either through software (ADC-READY bit in the General Status register, 0x1F) or hardware (DAV/ADC_RDY pin). To use the DAV/ADC_RDY pin as a READY status indicator, the pin must first be enabled through the DAVPIN-EN bit in register 0x11. Furthermore the ADC_RDY functionality must be selected by setting the DAVPIN-SEL bit in register 0x11 to '1'.

The conversion cycle is initiated by setting the ADC-TRIG bit to 1 in the DAC and ADC Trigger register (address 0x1C) which issues an ADC trigger signal. If the trigger signal is issued while the ADC is not in the READY state it is ignored.

Once the conversion cycle starts the ADC leaves the READY state. In direct-mode conversion upon completion of the first conversion sequence the ADC returns to the READY state and waits for a new trigger signal. Alternatively, in autonomous conversion upon completion of the first conversion another sequence is automatically started. Conversion of the selected channels occurs repeatedly until the conversion is stopped by issuing another trigger signal, at which point the ADC returns to the READY state.

The following ADC registers should only be updated while the ADC is not in a conversion cycle:

• Device configuration register (address 0x02)
• AMC configuration 0 register (address 0x10)
• AMC configuration 1 register (address 0x11)
• ADC MUX register (address 0x12)
• ALARMOUT configuration register (0x1B)
• Threshold registers (0x40 – 0x4D)
• Hysteresis registers (0x50 – 0x56)

After updating any of the configuration registers listed above, either a minimum 2 µs wait time or READY state must be ensured before issuing an ADC trigger signal.

Since the ADC is used for voltage, current, and temperature sensor conversions, all of which have significantly different update times, an interleaved conversion sequence is followed. The interleaved sequence ensures the wait time between measurement updates is minimized. Figure 48 illustrates the ADC conversion sequence with all input channels enabled and set to their fastest update time (CS-FILTER[2:0] = 000 and RT-SET[2:0] = 000 in the AMC Configuration register - 0x10).

Figure 48. ADC General Interleaved Sequence

Each ADC interleave step takes 200 µs and is segmented intro three sensing slots: temperature, voltage and current. The temperature slot is 24 µs long and allocates the temperature sensing channel conversions (internal temperature sensor and two remote temperature sensors) following the order LT → RT1 → RT2 → LT → ... If one of the temperature channels is not selected for conversion it is skipped. For example, if RT1 is not selected for conversion, the temperature slot conversion sequence is LT → RT2 → LT → ... Figure 48 illustrates the conversion sequence for the lowest remote temperature sensor update time, which is configured by setting RT-SET[2:0] = 000 in register 0x10. If a longer temperature sensor is selected to improve measurement accuracy a higher number of interleave steps is allocated for the remote temperature sensors.

The voltage slot takes 16 µs and allocates the four external inputs and four DAC monitoring internal inputs conversions. The external inputs, if enabled, are converted first. If none of the channels in a group (external or internal) are selected, no time is allocated for conversion of that group. However if at least one of the input channels in a group is enabled, five interleave steps (1 ms) are allocated regardless of the total number of input channels.

The current slot allocates the four current sensing channel conversions. The current slot is 160 µs long independent of how many current sense channels are enabled. The current sensors are updated on each interleave step (200 µs) when the CS-FILTER[2:0] set to 000 in register 0x10. If a longer current sense update time is selected to improve measurement accuracy a higher number of interleave steps is allocated for the current sense conversions.

The update time for all monitoring inputs is determined by the interleave sequence followed. Direct-mode conversions require an additional 40 µs of update time. In order to simplify synchronization, the AMC7834 provides a data-available signal through the DAV/ADC_RDY pin. The DAV/ADC_RDY pin must first be enabled through the DAVPIN-EN bit in register 0x11. Furthermore the DAV functionality must be selected by clearing the DAVPIN-SEL bit in register 0x11 to '0'.

In direct-mode conversion the DAV/ADC_RDY pin goes low after the conversion sequence has been completed. Additionally, in direct-mode conversion the data available flags in the General status register (address 0x1F) can be used to determine when new data is available for each data-available channel group. In autonomous conversion the DAV/ADC_RDY pin indicates when new data is available for each data-available channel group by issuing a 20 µs pulse (active low).

In both conversion methods the data-available function identifies six channel groups:

1. Current sense inputs: CS1 through CS4
2. External analog inputs: ADC1 through ADC4
3. Internal monitoring inputs: ADCINT1 through ADCINT4
4. Internal temperature sensor: LT
5. Remote temperature sensor 1: RT1
6. Remote temperature sensor 2: RT2

7.3.3.1 Internal Temperature Sensor

The AMC7834 device has an on-chip temperature sensor that measures the device die temperature. The temperature-sensor results are converted by the device ADC (see the Analog-to-Digital Converter (ADC) section for more information). If internal temperature sensor conversion is not needed, it can be disabled in the ADC MUX register (address 0x12). When disabled the temperature sensor output is not converted by the ADC.

The temperature sensor provides 0.25°C resolution over the device operating temperature range. Additionally, the AMC7834 internal temperature sensor is specified monotonic down to –55°C. The temperature value is stored in 12-bit two’s complement format in the LT-data register (address 0x2D).

Use Equation 4 and Equation 5 to calculate the positive or negative temperature according to the polarity of the temperature data MSB (0 = positive, 1 = negative).

Equation 4.

Equation 5.

7.3.3.2 Remote Temperature Sensors

The AMC7834 device includes two remote junction-temperature sensors. The remote sensing transistors can be a discrete, small-signal type transistor or a substrate transistor built within the power amplifier. These transistors are typically low-cost NPN- or PNP-type transistors such as the 2N3904 and 2N3906. Figure 49 shows the recommended connection for NPN and PNP transistors in diode configuration.

The AMC7834 device also allows PNP transistor configuration as shown in Figure 50. PNP transistor configuration for both remote temperature sensors is enabled by setting the RMT-GND-COLL bit to 1 in register 0x11.

Figure 49. NPN and PNP Diode Configuration

Figure 50. PNP Transistor Configuration

Errors in remote temperature sensor readings are typically the consequence of misalignment in the ideality factor and current excitation used by the AMC7834 versus the manufacturer-specified operating current for a given transistor. Some manufacturers specify a low-level (I_LOW) and high-level (I_HIGH) current for the temperature-sensing substrate transistors. The AMC7834 uses an I_LOW of 7 µA and I_HIGH of 112 µA and is designed to work with discrete transistors, such as the 2N3904 and SN3906. If an alternative transistor is used, the following conditions should be met:

1. Base-emitter voltage (V_BE) > 0.25 V at 7 µA for the highest sensed temperature
2. Base-emitter voltage (V_BE) < 1.20 V at 112 µA for the lowest sensed temperature
3. Base resistance < 100 Ω
4. Tight control of V_BE characteristics indicated by small variations in h_FE (50 to 150)

The ideality factor (η) is a measured characteristic of a remote temperature sensor diode as compared to an ideal one. The AMC7834 is trimmed for η = 1.008. If the selected remote sensing transistor's ideality factor is different, the effective η-factor should be adjusted at the system level.

Remote junction-temperature sensors are usually implemented in a noisy environment. Noise is most often created by fast digital signals and can corrupt measurements. A bypass capacitor placed differentially across the inputs of the remote temperature sensors can make the application more robust against unwanted coupled signals. If filtering is required, its time constant, including any routing resistance, should be limited to 5 µs or less. The combined series resistance on the remote temperature sensor pins must be less than 1 kΩ.

The two remote temperature sensor results are converted by the device ADC (see the Analog-to-Digital Converter (ADC) section for more information). The two remote temperature sensors can be disabled in the ADC MUX register (address 0x12). When disabled, the remote temperature sensor outputs are not converted by the ADC. The remote temperature values are stored in 12-bit two’s complement format in the RT-data registers (address 0x2E and 0x2F) using the same data format as the internal temperature sensor (see Table 3).

The AMC7834 device enables optimization of the remote temperature measurements by increasing the update time. The remote temperature-sensor update time is selected by the RT-SET[2:0] setting in register 0x10. Table 4 lists the total update time for the two remote temperature sensors with respect to the RT-SET[2:0] setting.

Optimal remote temperature sensor accuracy is achieved with the current-sense inputs disabled. In applications requiring simultaneous current-sensor and remote temperature sensor conversions it is recommended to implement external remote temperature conversion averaging to attain best accuracy results.

Table 5. Current Sense Digital Filter Configuration

7.3.6.1 ADC Internal Monitoring Input Out-of-Range Alarm

The AMC7834 device can provide out-of-range detection for the four internal ADC inputs monitoring the bipolar DAC outputs when operating in closed-loop mode. The ADCINT/CS-SELECT bit in register 0x1B must be cleared to 0 to enable out-of-range detection on the internal ADC inputs.

Figure 55 shows the out-of-range detection block. When the measurement is out-of-range, the corresponding alarm bit in the alarm status register is set to 1 to flag the out-of-range condition. The values in the ADCINTn/CSn upper and lower threshold registers (address 0x40 through 0x47) define the upper- and lower-bound thresholds for these inputs when the ADCINT/CS-SELECT bit in the ALARMOUT configuration register (address 0x1B) is cleared to 0.

Figure 55. ADC Monitoring Out-of-Range Alarm

7.3.6.2 Current-Sense Out-of-Range Alarm

The AMC7834 device is capable of providing out-of-range detection for the four current-sense inputs when operating in open-loop mode. The current-sense out-of-range detection is only active if the ADCINT/CS-SELECT bit in register 0x1B is set to 1.

Figure 56 shows the current sense detection block. When the measurement is out-of-range, the corresponding alarm bit in the alarm status register is set to 1 to flag the out-of-range condition. The values in the ADCINTx/CSx upper and lower threshold registers (address 0x40 through 0x47) define the upper- and lower-bound thresholds for these inputs when the ADCINT/CS-SELECT bit in the ALARMOUT configuration register (address 0x1B) is set to 1.

Figure 56. Current-Sense Out-of-Range Alarm

7.3.6.3 Temperature Sensors Out-of-Range Alarm

The AMC7834 device also includes high-limit or low-limit detection for the temperature sensors. Figure 57 shows the temperature detection block. The values in the temperature sensors upper and lower threshold registers (address 0x48 through 0x4D) set the limits for the temperature sensors. The temperature sensors can issue either a high alarm (HIGH-ALARM bit) or a low alarm (LOW-ALARM bit) in the alarm status register (address 0x1E) depending on whether the high or low thresholds were exceeded. To implement single, upper-bound threshold detection for the temperature sensors, the host processor can set the upper-bound threshold to the desired value and the lower-bound threshold to the default value. For lower-bound threshold detection, the host processor can set the lower-bound threshold to the desired value and the upper-bound threshold to the default value.

Figure 57. Temperature Out-of-Range Alarm

7.3.6.4 Bipolar DACs High Alarm

The AMC7834 device includes configurable upper-limit detection for the bipolar DACs in closed-loop mode. Figure 58 shows the alarm detection block. The values in the bipolar DAC upper threshold registers (address 0x4E through 0x4F) set a limit other than full-scale limit for the bipolar DACs. When a closed-loop controller attempts to set its bipolar DAC to a value exceeding the corresponding upper-threshold register, the DAC is instead updated with the threshold value and a DAC high-alarm is issued in the alarm status register.

Figure 58. Bipolar DAC High Alarm

7.3.6.5 AV_SS Detection Alarm

The device continuously monitors the AV_SS supply to ensure it is within the required operating threshold. By setting the PAON_AVSS bit to 1 in the AMC configuration 1 register (address 0x11) the AV_SS alarm can be set to automatically set the PA_ON pin to the OFF state and prevent it from getting configured back to the ON state unless the AV_SS alarm has been cleared.

7.3.6.6 AV_DD Detection Alarm

The device continuously monitors the AV_DD supply to ensure it is within the required operating threshold. An AV_DD alarm initiates a POR event which sets the PA_ON pin to the OFF state, bipolar DACs to the AV_SS clamp mode and auxiliary DACs to clamp mode.

7.3.6.7 Hysteresis

If a monitored signal is out of range and the alarm is enabled, the corresponding alarm bit is set to 1. However, the alarm condition is cleared only when the conversion result returns either a value lower than the high threshold register setting or higher than the low threshold register setting by the number of codes specified in the hysteresis setting (Figure 59). The hysteresis registers (address 0x50 through 0x56) store the hysteresis value for the programmable alarms. The hysteresis is a programmable value between 0 LSB to 127 LSB for the internal ADC monitoring and current-sense alarms and 0°C to 31°C for the temperature-sensor alarms.

Figure 59. Device Hysteresis

7.3.6.8 False-Alarm Protection

To prevent false alarms, an alarm event is only registered when the monitored signal is out of range for an N number of consecutive conversions. If the monitored signal returns to the normal range before N consecutive conversions, an alarm event is not issued. The false alarm factor, N, can be configured in the AMC configuration 1 register (address 0x11).

7.3.7.1 Internal Reference Operation

The AMC7834 device includes a 2.5 V bipolar transistor-based, precision bandgap reference. The internal reference is externally available at the REF_OUT pin and can be used to drive the ADC and eight DACs by connecting the REF_OUT pin to the REF_IN pin (see Figure 60). A 10-nF capacitor is recommended between REF_OUT and AGND for noise filtering. An external buffer amplifier with a high-impedance input must be used to drive any external load. A compensation capacitor (4.7 μF, typical) should be connected between the REF_CMP pin and the AGND4 pin.

Figure 60. Internal Reference Operation

7.3.7.2 External Reference Operation

The AMC7834 device can also operate from an external reference. The external reference can be applied to the REF_IN pin and is used to drive both the ADC and the eight DACs through separate buffers (see Figure 61). As with the internal-reference case a compensation capacitor (4.7 μF, typical) should be connected between the REF_CMP pin and the AGND4 pin. The REF_OUT pin can be left floating if unused.

Figure 61. External Reference Operation

Table 6. Open-Loop Mode Register Configuration

Table 7. Closed-Loop Mode Register Configuration

Table 8. Closed-Loop Settling Time

7.6.1.1 Power Mode Register (address = 0x02) [reset = 0x000]

7.6.2.1 Device ID Register (address = 0x04) [reset = 0x0C34]

7.6.2.2 Version ID Register (address = 0x06) [reset = 0x0001]

7.6.2.3 Vendor ID Register (address = 0x0C) [reset = 0x0451]

7.6.3.1 AMC Configuration 0 Register (address = 0x10) [reset = 0x0300]

Table 15. AMC Configuration 0 Field Descriptions

Bit	Field	Type	Reset	Description
15-13	Reserved	R/W	000	Reserved for factory use.
12	CMODE	R/W	0	0: Autonomous ADC conversion 1: Direct-mode ADC conversion
11	Reserved	R/W	0	Reserved for factory use.
10-8	CS-FILTER[2:0]	R/W	011	Current sense filter setting. Improves noise of current sensors measurements by trading off the update time. The digital filter has the transfer function: Equation 12. See Table 16 for its configuration.
7	Reserved	R/W	0	Reserved for factory use.
6-4	RT-SET[2:0]	R/W	000	Improves noise of the remote temperature sensors measurements by trading off the update time. See Table 17 for its configuration.
3-1	Reserved	R/W	000	Reserved for factory use.
0	LOOP-EN	R/W	0	When set to 1 enables closed-loop mode operation.

7.6.3.2 AMC Configuration 1 Register (address = 0x11) [reset = 0x036A]

7.6.3.3 ADC MUX Register (address = 0x12) [reset = 0x0000]

7.6.3.4 Closed Loop Settling Time Register (address = 0x14) [reset = 0x2222]

7.6.3.5 DAC Sync Register (address = 0x15) [reset = 0x0000]

7.6.3.6 DAC Range Register (address = 0x16) [reset = 0x0000]

7.6.4.1 CLAMP Configuration Register (address = 0x17) [reset = 0x003F]

7.6.4.2 SLEEP1 Configuration Register (address = 0x18) [reset = 0xFF00]

7.6.4.3 SLEEP2 Configuration Register (address = 0x19) [reset = 0xFF00]

7.6.4.4 ALARMOUT Clamp Register (address = 0x1A) [reset = 0x0000]

7.6.4.5 ALARMOUT Configuration Register (address = 0x1B) [reset = 0x0000]

7.6.5.1 DAC and ADC Trigger Register (address = 0x1C) [reset = 0x0000]

7.6.6.1 Software Reset Register (address = 0x1D) [reset = 0x0000]

7.6.7.1 Alarm Status Register (address = 0x1E) [reset = 0x0000]

7.6.7.2 General Status Register (address = 0x1F) [reset = 0x0000]

7.6.8.1 ADCn-Internal-Data Register (address = 0x20 to 0x23) [reset = 0x0000]

This register description applies to the internal monitoring inputs ADCINT1 through ADCINT4.

Table 33. ADCn-Internal-Data Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Reserved	R	0000	Reserved for factory use.
11–0	ADCINTn-DATA[11:0]	R	0x000	Stores the 12–bit ADCINTn conversion results in straight binary format. The corresponding voltage is given by: Equation 13.

7.6.8.2 ADCn-External-Data Register (address = 0x24 to 0x27) [reset = 0x0000]

This register description applies to the external inputs ADC1 through ADC4.

7.6.8.3 CSn-Data Register (address = 0x28 to 0x2B) [reset = 0x0000]

This register description applies to the current sense inputs CS1 through CS4.

7.6.8.4 LT-Data Register (address = 0x2D) [reset = 0x0000]

7.6.8.5 RTn–Data Register (address = 0x2E to 0x2F) [reset = 0x0000]

This register description applies to the remote temperature sense inputs RT1 and RT2.

7.6.9.1 DACn-Data Register (address = 0x30 to 0x33) [reset = 0x0000]

This register description applies to the bipolar DAC outputs DAC1 through DAC4.

7.6.9.2 AUXDACn-Data Register (address = 0x34 to 0x37) [reset = 0x0000]

This register description applies to the auxiliary DAC outputs AUXDAC1 through AUXDAC4.

7.6.10.1 ClosedLoopn Register (address = 0x38 to 0x3B) [reset = 0x0000]

This register description applies to the ClosedLoop1 through ClosedLoop4 registers.

Table 40. ClosedLoopn Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Reserved	R/W	0000	Reserved for factory use.
11–0	CLOSEDLOOPn[11:0]	R/W	0x000	Sets the target current for closed loop controller n through the following equation: Equation 14.

7.6.11.1 ADCINTn/CSn-Upper-Threshold Register (address = 0x40, 0x42, 0x44 and 0x46) [reset = 0x0FFF]

This register description applies to the upper threshold alarm registers for ADCINT1/CS1 through ADCINT4/CS4.

7.6.11.2 ADCINTn/CSn-Lower-Threshold Register (address = 0x41, 0x43, 0x45 and 0x47) [reset = 0x0000]

This register description applies to the lower threshold alarm registers for ADCINT1/CS1 through ADCINT4/CS4.

7.6.11.3 TS-Upper-Threshold Register (address = 0x48, 0x4A and 0x4C) [reset = 0x07FF]

This register description applies to the upper threshold alarm registers for the device temperature sensors: LT, RT1 and RT2.

7.6.11.4 TS-Lower-Threshold Register (address = 0x49, 0x4B and 0x4D) [reset = 0x0800]

This register description applies to the lower threshold alarm registers for the device temperature sensors: LT, RT1 and RT2.

7.6.11.5 DACnn-Upper-Threshold Register (address = 0x4E and 0x4F) [reset = 0x0FFF]

This register description applies to the upper threshold alarm registers for the bipolar DAC pairs DAC1/DAC2 and DAC3/DAC4.

7.6.12.1 ADCINTn/CSn-Hysteresis Register (address = 0x50 to 0x53) [reset = 0x0008]

This register description applies to the hysteresis registers for ADCINT1/CS1 through ADCINT4/CS4.

7.6.12.2 LT-Hysteresis Register (address = 0x54) [reset = 0x0008]

7.6.12.3 RTn–Hysteresis Register (address = 0x55 to 0x56) [reset = 0x0008]

This register description applies to the hysteresis registers for RT1 and RT2.

7.6.13.1 GPIO Register (address = 0x58) [reset = 0x000F]