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  • AMC80 System Hardware Monitor with Two-Wire and SMBus Serial Interface

    • SBOS559B May   2011  – October 2015 AMC80

      PRODUCTION DATA.  

  • CONTENTS
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  • AMC80 System Hardware Monitor with Two-Wire and SMBus Serial Interface
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Block Level Description
      2. 7.3.2 Temperature Measurement
        1. 7.3.2.1 Default Interrupt Mode
        2. 7.3.2.2 One-Time Interrupt Mode
        3. 7.3.2.3 Comparator Mode
      3. 7.3.3 Interrupt Structure
    4. 7.4 Programming
      1. 7.4.1 Interface and Control
    5. 7.5 Register Map
      1. 7.5.1  Configuration Register
      2. 7.5.2  Interrupt Status Registers
      3. 7.5.3  Interrupt Mask Registers
      4. 7.5.4  Fan Divisor/RST_OUT/OS Register
      5. 7.5.5  OS Configuration/Temperature Resolution Register
      6. 7.5.6  Conversion Rate Register
      7. 7.5.7  Voltage/Temperature Channel Disable Register
      8. 7.5.8  Input Mode Register
      9. 7.5.9  ADC Control Register
      10. 7.5.10 Conversion Rate Count Register
      11. 7.5.11 Value Ram Register
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Power-On
      2. 8.1.2 Analog Inputs
      3. 8.1.3 Fan Inputs
  9. 9 Device and Documentation Support
    1. 9.1 Community Resources
    2. 9.2 Trademarks
    3. 9.3 Electrostatic Discharge Caution
    4. 9.4 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
  11. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • PW|24
    • MPDS363A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • sbos559b_oa
  • sbos559b_pm
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
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DATA SHEET

AMC80 System Hardware Monitor with Two-Wire and SMBus Serial Interface

1 Features

  • 10-Bit ADC With Seven Analog Inputs
  • Fan-Speed Monitoring Inputs
  • Input Range/Resolution:
    • Default: 2.56 V/2.5 mV
    • Programmable: VDD/6 mV
  • Chassis Intrusion Detection Input
  • Interrupt Alarms:
    • Upper Over-Limit
    • Lower Under-Limit
  • Interrupt Status Register Input for External Temperature Sensors
  • Shutdown Mode
  • Programmable RST_OUT/OS
  • Pin Compatible with LM96080 and LM80
  • Package: 24-Pin TSSOP

2 Applications

  • Communications Equipment
  • Servers
  • Industrial and Medical Equipment
  • Storage Area Networks
  • Set-Top Boxes
  • Test and Measurement Equipment

3 Description

The AMC80 is a system hardware monitoring and control circuit that includes a seven-channel, 10-bit analog-to-digital converter (ADC), two programmable fan-speed monitors, and a two-wire interface. The AMC80 also includes programmable upper over-limit and lower under-limit alarms that activate when the programmed limits are exceeded.

The AMC80 can interface with both linear and digital temperature sensors. The 2.5-mV least significant bit (LSB) and 2.56-V input range can accept inputs from a linear sensor such as the TMP20. The BTI pin is used as an input from a digital sensor such as the TMP75. The AMC80 operates from a 3-V to 5.5-V supply voltage, has low supply current, and can be configured using a two-wire interface, thus making it ideal for a wide range of applications.

The AMC80 is available in a 24-lead TSSOP package and is fully specified over the –40°C to +125°C temperature range.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
AMC80 TSSOP (24) 7.80 mm × 4.40 mm
  1. For all available packages, see the package option addendum at the end of the data sheet.

Simplified Schematic

AMC80 fbd_bos559.gif

4 Revision History

Changes from A Revision (January 2012) to B Revision

  • Changed INT pin descriptionGo
  • Added pins to input voltage range in Absolute Maximum Ratings tableGo
  • Added ESD Ratings tableGo
  • Added new note 1 to Timing Requirements tableGo
  • Added Detailed Description sectionGo
  • Added Application and Implementation sectionGo
  • Added Device and Documentation Support sectionGo

Changes from * Revision (May 2011) to A Revision

  • Added SMBus timeout parameter to Electrical CharacteristicsGo
  • Changed Bit 0 = '1' in Table 10Go

5 Pin Configuration and Functions

PW Package
24-Pin TSSOP
Top View
AMC80 po_bos559.gif

Pin Functions

PIN I/O TYPE DESCRIPTION
NO. NAME
1 INT_IN Input Digital Interrupt input pin. An active low input that extends the INT_IN signal to the INT output of the AMC80.
2 SDA I/O Digital Serial bus data line for SMBus, open-drain; requires pull-up resistor.
3 SCL I/O Digital Serial bus clock line for SMBus, open-drain; requires pull-up resistor.
4 FAN1 Input Digital Fan tachometer input pin
5 FAN2 Input Digital Fan tachometer input pin
6 BTI Input Digital Board temperature interrupt pin. BTI is driven by the over-temperature shutdown (OS) outputs of the additional temperature sensors. This pin has an internal 10-kΩ pull-up resistor.
7 GPI(CI) Input Digital General-purpose input pin (chassis interrupt). An active high interrupt input pin to latch a chassis interrupt event.
8 DGND Power Analog Digital ground.
9 V+ Power Analog Positive supply voltage (3V to 5.5V).
10 INT Output Digital Non-maskable interrupt (active high, PMOS, push-pull) or interrupt request (active low, NMOS, push-pull) pin. The INT pin becomes active when INT_IN, BTI, or GPI interrupts. This pin does not require a pullup resistor to V+.
11 GPO Output Digital General-purpose output pin. GPO is an active low, NMOS, open-drain output. This pin is intended to drive an external power PMOS for software power control or to control power to a cooling fan.
12 NTEST_IN/RESET_IN Input Digital This pin is an active-low input that enables NAND tree board-level connectivity testing. The AMC80 resets to its power-on state when NAND tree connectivity is enabled.
13 RST_OUT/OS Output Digital This pin is an NMOS open-drain output. RST_OUT provides a master reset to devices connected to this line. OS is dedicated to the temperature reading alarm.
14 AGND Power Analog Analog ground. This pin must be tied to a low-noise analog ground plane for optimum performance.
15 CH6 Input Analog Analog input channel 6
16 CH5 Input Analog Analog input channel 5
17 CH4 Input Analog Analog input channel 4
18 CH3 Input Analog Analog input channel 3
19 CH2 Input Analog Analog input channel 2
20 CH1 Input Analog Analog input channel 1
21 CH0 Input Analog Analog input channel 0
22 A0/NTEST_OUT I/O Digital The lowest order bit of the serial bus address. During a NAND tree test for ATE board-level connectivity, this pin functions as an output.
23 A1 Input Digital Address pin 1
24 A2 Input Digital Address pin 2

6 Specifications

6.1 Absolute Maximum Ratings(1)

Over operating free-air temperature range, unless otherwise noted.
MIN MAX UNIT
Power-supply voltage range, V+ –0.3 7 V
Input voltage range, VIN Pins 6, 10, 15, 16, 17, 18, 19, 20, 21, 22, 24 –0.3 (V+) + 0.3 V
Pins 1, 2, 3, 4, 5, 7, 9, 11, 12, 13, 23 –0.3 7
Input current, IIN 10 mA
Operating temperature range, TA –55 127 °C
Junction temperature range, TJ max 150 °C
Storage temperature range, TSTG –65 150 °C
(1) Stresses above these ratings my cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
Machine model (MM) ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. ance.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply voltage range, V+ 3 5.5 V
Input voltage range, VIN –0.05 (V+) + 0.05 V
Operating temperature range, TA –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) AMC80 UNIT
PW (TSSOP)
24 PINS
RθJA Junction-to-ambient thermal resistance 100.72 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 31.4 °C/W
RθJB Junction-to-board thermal resistance 54.7 °C/W
ψJT Junction-to-top characterization parameter 1.0 °C/W
ψJB Junction-to-board characterization parameter 54.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

At TA –40°C to +125°C and V+ = 3 V to 5.5 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUTS
VIH Input high voltage 2 V
VIL Input low voltage 0.8 V
VHYS Hysteresis voltage V+ = 3.3 V 0.23 V
V+ = 5 V 0.33 V
IIH Input high current VIH = V+, all pins except BTI –1 –0.005 µA
VIH = V+, BTI pin –10 –1 µA
IIL Input low current VIL = 0 V, all pins except BTI 0.005 1 µA
VIL = 0 V, V+ = 5.5 V, BTI pin 2 mA
CIN Input capacitance 20 pF
ANALOG INPUTS
VIN Input voltage range Default 0 2.56 V
Programmable 0 V+ V
IL-ON Input leakage current (on) ±0.005 µA
IL-OFF Input leakage current (off) ±0.005 µA
RIN Input resistance 2 10 kΩ
DIGITAL OUTPUTS (A0/NTEST_OUT, INT)
VOH Output high voltage IOUT = 3 mA/5 mA, V+ = 3 V/4.5 V 2.4 V
VOL Output low voltage IOUT = 3 mA/5 mA, V+ = 3 V/4.5 V 0.4 V
DIGITAL OPEN-DRAIN OUTPUTS (GPO, RST_OUT/OS, GPI/CI, SDA)
VOL Output low voltage IOUT = 3 mA/5 mA, V+ = 3 V/4.5 V,
all pins except SDA		 0.4 V
IOUT = 4 mA, V+ = 3 V, SDA pin 0.4
IOH Output high current VOUT = V+ 0.005 1 µA
tw Pulse duration RST_OUT/OS, GPI/CI 10 22.5 ms
SMBus
SMBus timeout(1) 28 35 ms
TEMPERATURE ERROR
TE Temperature error TA = –40°C to +125°C ±3 °C
TA = –25°C to +100°C ±2 °C
TR Temperature resolution 0.0625 °C
ANALOG-TO-DIGITAL CONVERTER
VR Resolution VIN = 2.56 V 2.5 mV
VIN = V+ 6
DNL Differential linearity –1 1 LSB(2)
ADCERR Total unadjusted error(3) –1% 1%
PSRR Power supply rejection ratio ±0.0008%
tC(4) Total conversion time 662 728 810 ms
FAN RPM-TO-DIGITAL CONVERTER
FANERR Fan RPM error –10% 10%
fCLK Internal clock frequency 20.2 22.5 24.8 kHz
FANRPM FAN1 and FAN2 nominal input RPM Divisor = 1, fan count = 153 8800 RPM
Divisor = 2, fan count = 153 4400
Divisor = 3, fan count = 153 2200
Divisor = 4, fan count = 153 1100
FSC Full-scale count 255 Counts
POWER SUPPLY
V+ Specified voltage range 3 5.5 V
IQA Quiescent current, average V+ = 5.5 V 100 µA
V+ = 3.8 V 25
IQSD Quiescent current, shutdown mode V+ = 5.5 V 100 µA
V+ = 3.8 V 25
TEMPERATURE
TA Specified range -40 125 °C
(1) The SMBus timeout in the AMC80 resets the interface anytime SCL or SDA is low for over 28 ms.
(2) LSB means least significant bit.
(3) Total unadjusted error contains offset, gain, and linearity errors of the ADC.
(4) Total conversion time contains the temperature conversion, the seven analog input voltage conversions, and the two tachometer readings.

6.6 Timing Requirements

At TA –40°C to +125°C and VS = 3V to 5.5V, unless otherwise noted.
FAST MODE(1) HIGH-SPEED MODE(1) UNIT
MIN MAX MIN MAX
f(SCL) SCL operating frequency 10 400 10 3400 kHz
t(BUF) Bus free time between STOP and START conditions 600 160 ns
t(HDSTA) Hold time after repeated START condition. After this period, the first clock is generated. 600 160 ns
t(SUSTA) Repeated START condition setup time 600 160 ns
t(SUSTO) STOP condition setup time 600 160 ns
t(HDDAT) Data hold time 0(2) 0(3) ns
t(SUDAT) Data setup time 100 10 ns
t(LOW) Clock low period 1300 160 ns
t(HIGH) Clock high period 600 60 ns
tR Clock/Data input rise time 300 160 ns
tF Clock/Data input fall time 300 160 ns
(1) Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not specified and not production tested.
(2) For cases when the fall time of SCL is less than 20 ns and/or the rise time or fall time of SDA is less than 20 ns, the hold time should be greater than 20 ns.
(3) For cases when the fall time of SCL is less than 10 ns and/or the rise or fall time of SDA is less than 10 ns, the hold time should be greater than 10 ns.
AMC80 tim_two-wire_bos559.gif Figure 1. Serial Bus Interface Timing

6.7 Typical Characteristics

At TA = +25°C and V+ = 3 V to 5.5 V, unless otherwise noted.
AMC80 tc_iqa-v_bos559.gif
Figure 2. Average Quiescent Current vs Supply Voltage
AMC80 tc_iqt-v_bos559.gif
Figure 4. Quiescent Current During Temperature Conversion vs Supply Voltage
AMC80 tc_tmp_error-v_bos559.gif
Figure 6. Temperature Error vs Supply Voltage
AMC80 tc_iqv-v_bos559.gif
Figure 3. Quiescent Current During Voltage Conversion vs Supply Voltage
AMC80 tc_iqsd-v_bos559.gif
Figure 5. Quiescent Current During Shutdown vs Supply Voltage

 
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