SPRS971D August   2016  – March 2020 AMIC110

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
      1. 4.1.1 ZCE Package Pin Maps (Top View)
      2. 4.1.2 ZCZ Package Pin Maps (Top View)
        1. Table 4-1 ZCZ Pin Map [Section Left - Top View]
        2. Table 4-2 ZCZ Pin Map [Section Middle - Top View]
        3. Table 4-3 ZCZ Pin Map [Section Right - Top View]
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1 External Memory Interfaces
      2. 4.3.2 General Purpose IOs
      3. 4.3.3 Miscellaneous
        1. 4.3.3.1 eCAP
        2. 4.3.3.2 eHRPWM
        3. 4.3.3.3 eQEP
        4. 4.3.3.4 Timer
      4. 4.3.4 PRU-ICSS
        1. 4.3.4.1 PRU0
        2. 4.3.4.2 PRU1
      5. 4.3.5 Removable Media Interfaces
      6. 4.3.6 Serial Communication Interfaces
        1. 4.3.6.1 CAN
        2. 4.3.6.2 GEMAC_CPSW
        3. 4.3.6.3 I2C
        4. 4.3.6.4 McASP
        5. 4.3.6.5 SPI
        6. 4.3.6.6 UART
        7. 4.3.6.7 USB
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Operating Performance Points (OPPs)
    5. 5.5  Recommended Operating Conditions
    6. 5.6  Power Consumption Summary
    7. 5.7  DC Electrical Characteristics
    8. 5.8  Thermal Resistance Characteristics for ZCE and ZCZ Packages
    9. 5.9  External Capacitors
      1. 5.9.1 Voltage Decoupling Capacitors
        1. 5.9.1.1 Core Voltage Decoupling Capacitors
        2. 5.9.1.2 I/O and Analog Voltage Decoupling Capacitors
      2. 5.9.2 Output Capacitors
    10. 5.10 Touch Screen Controller and Analog-to-Digital Subsystem Electrical Parameters
  6. 6Power and Clocking
    1. 6.1 Power Supplies
      1. 6.1.1 Power Supply Slew Rate Requirement
      2. 6.1.2 Power-Down Sequencing
      3. 6.1.3 VDD_MPU_MON Connections
      4. 6.1.4 Digital Phase-Locked Loop Power Supply Requirements
    2. 6.2 Clock Specifications
      1. 6.2.1 Input Clock Specifications
      2. 6.2.2 Input Clock Requirements
        1. 6.2.2.1 OSC0 Internal Oscillator Clock Source
          1. Table 6-2 OSC0 Crystal Circuit Requirements
          2. Table 6-3 OSC0 Crystal Circuit Characteristics
        2. 6.2.2.2 OSC0 LVCMOS Digital Clock Source
        3. 6.2.2.3 OSC1 Internal Oscillator Clock Source
          1. Table 6-5 OSC1 Crystal Circuit Requirements
          2. Table 6-6 OSC1 Crystal Circuit Characteristics
        4. 6.2.2.4 OSC1 LVCMOS Digital Clock Source
        5. 6.2.2.5 OSC1 Not Used
      3. 6.2.3 Output Clock Specifications
      4. 6.2.4 Output Clock Characteristics
        1. 6.2.4.1 CLKOUT1
        2. 6.2.4.2 CLKOUT2
  7. 7Peripheral Information and Timings
    1. 7.1  Parameter Information
      1. 7.1.1 Timing Parameters and Board Routing Analysis
    2. 7.2  Recommended Clock and Control Signal Transition Behavior
    3. 7.3  OPP50 Support
    4. 7.4  Controller Area Network (CAN)
      1. 7.4.1 DCAN Electrical Data and Timing
        1. Table 7-1 DCAN Timing Conditions
        2. Table 7-2 Timing Requirements for DCANx Receive
        3. Table 7-3 Switching Characteristics for DCANx Transmit
    5. 7.5  DMTimer
      1. 7.5.1 DMTimer Electrical Data and Timing
        1. Table 7-4 DMTimer Timing Conditions
        2. Table 7-5 Timing Requirements for DMTimer [1-7]
        3. Table 7-6 Switching Characteristics for DMTimer [4-7]
    6. 7.6  Ethernet Media Access Controller (EMAC) and Switch
      1. 7.6.1 EMAC and Switch Electrical Data and Timing
        1. Table 7-7 EMAC and Switch Timing Conditions
        2. 7.6.1.1   EMAC/Switch MDIO Electrical Data and Timing
          1. Table 7-8  Timing Requirements for MDIO_DATA
          2. Table 7-9  Switching Characteristics for MDIO_CLK
          3. Table 7-10 Switching Characteristics for MDIO_DATA
        3. 7.6.1.2   EMAC and Switch MII Electrical Data and Timing
          1. Table 7-11 Timing Requirements for GMII[x]_RXCLK - MII Mode
          2. Table 7-12 Timing Requirements for GMII[x]_TXCLK - MII Mode
          3. Table 7-13 Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode
          4. Table 7-14 Switching Characteristics for GMII[x]_TXD[3:0], and GMII[x]_TXEN - MII Mode
        4. 7.6.1.3   EMAC and Switch RMII Electrical Data and Timing
          1. Table 7-15 Timing Requirements for RMII[x]_REFCLK - RMII Mode
          2. Table 7-16 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
          3. Table 7-17 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
        5. 7.6.1.4   EMAC and Switch RGMII Electrical Data and Timing
          1. Table 7-18 Timing Requirements for RGMII[x]_RCLK - RGMII Mode
          2. Table 7-19 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
          3. Table 7-20 Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
          4. Table 7-21 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
    7. 7.7  External Memory Interfaces
      1. 7.7.1 General-Purpose Memory Controller (GPMC)
        1. 7.7.1.1 GPMC and NOR Flash—Synchronous Mode
          1. Table 7-22 GPMC and NOR Flash Timing Conditions—Synchronous Mode
          2. Table 7-23 GPMC and NOR Flash Timing Requirements—Synchronous Mode
          3. Table 7-24 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
        2. 7.7.1.2 GPMC and NOR Flash—Asynchronous Mode
          1. Table 7-25 GPMC and NOR Flash Timing Conditions—Asynchronous Mode
          2. Table 7-26 GPMC and NOR Flash Internal Timing Requirements—Asynchronous Mode
          3. Table 7-27 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
          4. Table 7-28 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
        3. 7.7.1.3 GPMC and NAND Flash—Asynchronous Mode
          1. Table 7-29 GPMC and NAND Flash Timing Conditions—Asynchronous Mode
          2. Table 7-30 GPMC and NAND Flash Internal Timing Requirements—Asynchronous Mode
          3. Table 7-31 GPMC and NAND Flash Timing Requirements—Asynchronous Mode
          4. Table 7-32 GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
      2. 7.7.2 mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface
        1. 7.7.2.1 mDDR (LPDDR) Routing Guidelines
          1. 7.7.2.1.1 Board Designs
          2. 7.7.2.1.2 LPDDR Interface
            1. 7.7.2.1.2.1 LPDDR Interface Schematic
            2. 7.7.2.1.2.2 Compatible JEDEC LPDDR Devices
              1. Table 7-34 Compatible JEDEC LPDDR Devices (Per Interface)
            3. 7.7.2.1.2.3 PCB Stackup
            4. 7.7.2.1.2.4 Placement
            5. 7.7.2.1.2.5 LPDDR Keepout Region
            6. 7.7.2.1.2.6 Bulk Bypass Capacitors
            7. 7.7.2.1.2.7 High-Speed Bypass Capacitors
            8. 7.7.2.1.2.8 Net Classes
            9. 7.7.2.1.2.9 LPDDR Signal Termination
          3. 7.7.2.1.3 LPDDR CK and ADDR_CTRL Routing
        2. 7.7.2.2 DDR2 Routing Guidelines
          1. 7.7.2.2.1 Board Designs
          2. 7.7.2.2.2 DDR2 Interface
            1. 7.7.2.2.2.1  DDR2 Interface Schematic
            2. 7.7.2.2.2.2  Compatible JEDEC DDR2 Devices
              1. Table 7-46 Compatible JEDEC DDR2 Devices (Per Interface)
            3. 7.7.2.2.2.3  PCB Stackup
            4. 7.7.2.2.2.4  Placement
            5. 7.7.2.2.2.5  DDR2 Keepout Region
            6. 7.7.2.2.2.6  Bulk Bypass Capacitors
            7. 7.7.2.2.2.7  High-Speed (HS) Bypass Capacitors
            8. 7.7.2.2.2.8  Net Classes
            9. 7.7.2.2.2.9  DDR2 Signal Termination
            10. 7.7.2.2.2.10 DDR_VREF Routing
          3. 7.7.2.2.3 DDR2 CK and ADDR_CTRL Routing
        3. 7.7.2.3 DDR3 and DDR3L Routing Guidelines
          1. 7.7.2.3.1 Board Designs
            1. 7.7.2.3.1.1 DDR3 versus DDR2
          2. 7.7.2.3.2 DDR3 Device Combinations
          3. 7.7.2.3.3 DDR3 Interface
            1. 7.7.2.3.3.1  DDR3 Interface Schematic
            2. 7.7.2.3.3.2  Compatible JEDEC DDR3 Devices
            3. 7.7.2.3.3.3  PCB Stackup
            4. 7.7.2.3.3.4  Placement
            5. 7.7.2.3.3.5  DDR3 Keepout Region
            6. 7.7.2.3.3.6  Bulk Bypass Capacitors
            7. 7.7.2.3.3.7  High-Speed Bypass Capacitors
              1. 7.7.2.3.3.7.1 Return Current Bypass Capacitors
            8. 7.7.2.3.3.8  Net Classes
            9. 7.7.2.3.3.9  DDR3 Signal Termination
            10. 7.7.2.3.3.10 DDR_VREF Routing
            11. 7.7.2.3.3.11 VTT
          4. 7.7.2.3.4 DDR3 CK and ADDR_CTRL Topologies and Routing Definition
            1. 7.7.2.3.4.1 Two DDR3 Devices
              1. 7.7.2.3.4.1.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
              2. 7.7.2.3.4.1.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
            2. 7.7.2.3.4.2 One DDR3 Device
              1. 7.7.2.3.4.2.1 CK and ADDR_CTRL Topologies, One DDR3 Device
              2. 7.7.2.3.4.2.2 CK and ADDR_CTRL Routing, One DDR3 Device
          5. 7.7.2.3.5 Data Topologies and Routing Definition
            1. 7.7.2.3.5.1 DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices
            2. 7.7.2.3.5.2 DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices
          6. 7.7.2.3.6 Routing Specification
            1. 7.7.2.3.6.1 CK and ADDR_CTRL Routing Specification
            2. 7.7.2.3.6.2 DQS[x] and DQ[x] Routing Specification
    8. 7.8  I2C
      1. 7.8.1 I2C Electrical Data and Timing
        1. Table 7-70 I2C Timing Conditions – Slave Mode
        2. Table 7-71 Timing Requirements for I2C Input Timings
        3. Table 7-72 Switching Characteristics for I2C Output Timings
    9. 7.9  JTAG Electrical Data and Timing
      1. Table 7-73 JTAG Timing Conditions
      2. Table 7-74 Timing Requirements for JTAG
      3. Table 7-75 Switching Characteristics for JTAG
    10. 7.10 LCD Controller (LCDC)
    11. 7.11 Multichannel Audio Serial Port (McASP)
      1. 7.11.1 McASP Device-Specific Information
      2. 7.11.2 McASP Electrical Data and Timing
        1. Table 7-76 McASP Timing Conditions
        2. Table 7-77 Timing Requirements for McASP
        3. Table 7-78 Switching Characteristics for McASP
    12. 7.12 Multichannel Serial Port Interface (McSPI)
      1. 7.12.1 McSPI Electrical Data and Timing
        1. 7.12.1.1 McSPI—Slave Mode
          1. Table 7-79 McSPI Timing Conditions – Slave Mode
          2. Table 7-80 Timing Requirements for McSPI Input Timings—Slave Mode
          3. Table 7-81 Switching Characteristics for McSPI Output Timings—Slave Mode
        2. 7.12.1.2 McSPI—Master Mode
          1. Table 7-82 McSPI Timing Conditions – Master Mode
          2. Table 7-83 Timing Requirements for McSPI Input Timings – Master Mode
          3. Table 7-84 Switching Characteristics for McSPI Output Timings – Master Mode
    13. 7.13 Multimedia Card (MMC) Interface
      1. 7.13.1 MMC Electrical Data and Timing
        1. Table 7-85 MMC Timing Conditions
        2. Table 7-86 Timing Requirements for MMC[x]_CMD and MMC[x]_DAT[7:0]
        3. Table 7-87 Switching Characteristics for MMC[x]_CLK
        4. Table 7-88 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—Standard Mode
        5. Table 7-89 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—High-Speed Mode
    14. 7.14 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
      1. 7.14.1 Programmable Real-Time Unit (PRU-ICSS PRU)
        1. Table 7-90 PRU-ICSS PRU Timing Conditions
        2. 7.14.1.1   PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
          1. Table 7-91 PRU-ICSS PRU Timing Requirements - Direct Input Mode
          2. Table 7-92 PRU-ICSS PRU Switching Requirements – Direct Output Mode
        3. 7.14.1.2   PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
          1. Table 7-93 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
        4. 7.14.1.3   PRU-ICSS PRU Shift Mode Electrical Data and Timing
          1. Table 7-94 PRU-ICSS PRU Timing Requirements – Shift In Mode
          2. Table 7-95 PRU-ICSS PRU Switching Requirements - Shift Out Mode
      2. 7.14.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
        1. Table 7-96 PRU-ICSS ECAT Timing Conditions
        2. 7.14.2.1   PRU-ICSS ECAT Electrical Data and Timing
          1. Table 7-97  PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
          2. Table 7-98  PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
          3. Table 7-99  PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
          4. Table 7-100 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
          5. Table 7-101 PRU-ICSS ECAT Switching Requirements - Digital I/Os
      3. 7.14.3 PRU-ICSS MII_RT and Switch
        1. Table 7-102 PRU-ICSS MII_RT Switch Timing Conditions
        2. 7.14.3.1    PRU-ICSS MDIO Electrical Data and Timing
          1. Table 7-103 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
          2. Table 7-104 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
          3. Table 7-105 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
        3. 7.14.3.2    PRU-ICSS MII_RT Electrical Data and Timing
          1. Table 7-106 PRU-ICSS MII_RT Timing Requirements – MII_RXCLK
          2. Table 7-107 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
          3. Table 7-108 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
          4. Table 7-109 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
      4. 7.14.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
        1. Table 7-110 UART Timing Conditions
        2. Table 7-111 Timing Requirements for PRU-ICSS UART Receive
        3. Table 7-112 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
    15. 7.15 Universal Asynchronous Receiver Transmitter (UART)
      1. 7.15.1 UART Electrical Data and Timing
        1. Table 7-113 UART Timing Conditions
        2. Table 7-114 Timing Requirements for UARTx Receive
        3. Table 7-115 Switching Characteristics for UARTx Transmit
      2. 7.15.2 UART IrDA Interface
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Via Channel
    2. 9.2 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZCZ|324
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.2 Pin Attributes

The AM335x and AMIC110 Sitara Processors Technical Reference Manual and this document may reference internal signal names when discussing peripheral input and output signals because many of the AMIC110 package terminals can be multiplexed to one of several peripheral signals. The following table has a Pin Name column that lists all device terminal names and a Signal Name column that lists all internal signal names multiplexed to each terminal which provides a cross reference of internal signal names to terminal names. This table also identifies other important terminal characteristics.

  1. BALL NUMBER: Package ball numbers associated with each signals.
  2. PIN NAME: The name of the package pin or terminal.
    Note: The table does not take into account subsystem terminal multiplexing options.
  3. SIGNAL NAME: The signal name for that pin in the mode being used.
  4. MODE: Multiplexing mode number.
    1. Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the terminal corresponds to the name of the terminal. There is always a function mapped on the primary mode. Notice that primary mode is not necessarily the default mode.

      2. Note: The default mode is the mode at the release of the reset; also see the RESET REL. MODE column.

    2. Modes 1 to 7 are possible modes for alternate functions. On each terminal, some modes are effectively used for alternate functions, while some modes are not used and do not correspond to a functional configuration.
  5. TYPE: Signal direction
    • I = Input
    • O = Output
    • I/O = Input and Output
    • D = Open drain
    • DS = Differential
    • A = Analog
    • PWR = Power
    • GND = Ground

      • Note: In the safe_mode, the buffer is configured in high-impedance.

  6. BALL RESET STATE: State of the terminal while the active low PWRONRSTn terminal is low.
    • 0: The buffer drives VOL (pulldown or pullup resistor not activated)
      0(PD): The buffer drives VOL with an active pulldown resistor
    • 1: The buffer drives VOH (pulldown or pullup resistor not activated)
      1(PU): The buffer drives VOH with an active pullup resistor
    • Z: High-impedance
    • L: High-impedance with an active pulldown resistor
    • H : High-impedance with an active pullup resistor
  7. BALL RESET REL. STATE: State of the terminal after the active low PWRONRSTn terminal transitions from low to high.
    • 0: The buffer drives VOL (pulldown or pullup resistor not activated)
      0(PD): The buffer drives VOL with an active pulldown resistor
    • 1: The buffer drives VOH (pulldown or pullup resistor not activated)
      1(PU): The buffer drives VOH with an active pullup resistor
    • Z: High-impedance.
    • L: High-impedance with an active pulldown resistor
    • H : High-impedance with an active pullup resistor
  8. RESET REL. MODE: The mode is automatically configured after the active low PWRONRSTn terminal transitions from low to high.
  9. POWER: The voltage supply that powers the I/O buffers of the terminal.
  10. HYS: Indicates if the input buffer is with hysteresis.
  11. BUFFER STRENGTH: Drive strength of the associated output buffer.
  12. PULLUP OR PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.
  13. I/O CELL: I/O cell information.

    14. Note: Configuring two terminals to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration.

Table 4-4 Pin Attributes (ZCZ Package)

ZCZ BALL NUMBER [1] PIN NAME [2] SIGNAL NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] ZCZ POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULLUP /DOWN TYPE [12] I/O CELL [13]
B6 AIN0 AIN0 0 A (23) Z Z 0 VDDA_ADC NA 25 NA Analog
C7 AIN1 AIN1 0 A (22) Z Z 0 VDDA_ADC NA 25 NA Analog
B7 AIN2 AIN2 0 A (22) Z Z 0 VDDA_ADC NA 25 NA Analog
A7 AIN3 AIN3 0 A (21) Z Z 0 VDDA_ADC NA 25 NA Analog
C8 AIN4 AIN4 0 A (21) Z Z 0 VDDA_ADC NA 25 NA Analog
B8 AIN5 AIN5 0 A Z Z 0 VDDA_ADC NA NA NA Analog
A8 AIN6 AIN6 0 A Z Z 0 VDDA_ADC NA NA NA Analog
C9 AIN7 AIN7 0 A Z Z 0 VDDA_ADC NA NA NA Analog
C10 CAP_VBB_MPU CAP_VBB_MPU NA A
D6 CAP_VDD_RTC CAP_VDD_RTC NA A
D9 CAP_VDD_SRAM_CORE CAP_VDD_SRAM_CORE NA A
D11 CAP_VDD_SRAM_MPU CAP_VDD_SRAM_MPU NA A
F3 DDR_A0 ddr_a0 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
H1 DDR_A1 ddr_a1 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
E4 DDR_A2 ddr_a2 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
C3 DDR_A3 ddr_a3 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
C2 DDR_A4 ddr_a4 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
B1 DDR_A5 ddr_a5 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
D5 DDR_A6 ddr_a6 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
E2 DDR_A7 ddr_a7 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
D4 DDR_A8 ddr_a8 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
C1 DDR_A9 ddr_a9 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
F4 DDR_A10 ddr_a10 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
F2 DDR_A11 ddr_a11 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
E3 DDR_A12 ddr_a12 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
H3 DDR_A13 ddr_a13 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
H4 DDR_A14 ddr_a14 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
D3 DDR_A15 ddr_a15 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
C4 DDR_BA0 ddr_ba0 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
E1 DDR_BA1 ddr_ba1 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
B3 DDR_BA2 ddr_ba2 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
F1 DDR_CASn ddr_casn 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
D2 DDR_CK ddr_ck 0 O L 0 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
G3 DDR_CKE ddr_cke 0 O L 0 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
D1 DDR_CKn ddr_nck 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
H2 DDR_CSn0 ddr_csn0 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
M3 DDR_D0 ddr_d0 0 I/O L Z 0 VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
M4 DDR_D1 ddr_d1 0 I/O L Z 0 VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
N1 DDR_D2 ddr_d2 0 I/O L Z 0 VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
N2 DDR_D3 ddr_d3 0 I/O L Z 0 VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
N3 DDR_D4 ddr_d4 0 I/O L Z 0 VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
N4 DDR_D5 ddr_d5 0 I/O L Z 0 VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
P3 DDR_D6 ddr_d6 0 I/O L Z 0 VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
P4 DDR_D7 ddr_d7 0 I/O L Z 0 VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
J1 DDR_D8 ddr_d8 0 I/O L Z 0 VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
K1 DDR_D9 ddr_d9 0 I/O L Z 0 VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
K2 DDR_D10 ddr_d10 0 I/O L Z 0 VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
K3 DDR_D11 ddr_d11 0 I/O L Z 0 VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
K4 DDR_D12 ddr_d12 0 I/O L Z 0 VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
L3 DDR_D13 ddr_d13 0 I/O L Z 0 VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
L4 DDR_D14 ddr_d14 0 I/O L Z 0 VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
M1 DDR_D15 ddr_d15 0 I/O L Z 0 VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
M2 DDR_DQM0 ddr_dqm0 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
J2 DDR_DQM1 ddr_dqm1 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
P1 DDR_DQS0 ddr_dqs0 0 I/O L Z 0 VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
L1 DDR_DQS1 ddr_dqs1 0 I/O L Z 0 VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
P2 DDR_DQSn0 ddr_dqsn0 0 I/O H Z 0 VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
L2 DDR_DQSn1 ddr_dqsn1 0 I/O H Z 0 VDDS_DDR Yes 8 PU/PD LVCMOS/SSTL/HSTL
G1 DDR_ODT ddr_odt 0 O L 0 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
G4 DDR_RASn ddr_rasn 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
G2 DDR_RESETn ddr_resetn 0 O L 0 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
J4 DDR_VREF ddr_vref 0 A (19) NA NA NA VDDS_DDR NA NA NA Analog
J3 DDR_VTP ddr_vtp 0 I (20) NA NA NA VDDS_DDR NA NA NA Analog
B2 DDR_WEn ddr_wen 0 O H 1 0 VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/HSTL
C18 ECAP0_IN_PWM0_OUT eCAP0_in_PWM0_out (15) 0 I/O Z L 7 VDDSHV6 Yes 4 PU/PD LVCMOS
uart3_txd 1 O
spi1_cs1 2 I/O
pr1_ecap0_ecap_capin_apwm_o 3 I/O
spi1_sclk 4 I/O
mmc0_sdwp 5 I
xdma_event_intr2 6 I
gpio0_7 7 I/O
C14 EMU0 EMU0 0 I/O H H 0 VDDSHV6 Yes 6 PU/PD LVCMOS
gpio3_7 7 I/O
B14 EMU1 EMU1 0 I/O H H 0 VDDSHV6 Yes 6 PU/PD LVCMOS
gpio3_8 7 I/O
B18 EXTINTn nNMI 0 I Z H 0 VDDSHV6 Yes NA PU/PD LVCMOS
C5 EXT_WAKEUP EXT_WAKEUP 0 I L Z 0 VDDS_RTC Yes NA NA LVCMOS
R13 GPMC_A0 gpmc_a0 0 O L L 7 VDDSHV3 Yes 6 PU/PD LVCMOS
gpmc_a16 4 O
pr1_mii_mt1_clk 5 I
ehrpwm1_tripzone_input 6 I
gpio1_16 7 I/O
V14 GPMC_A1 gpmc_a1 0 O L L 7 VDDSHV3 Yes 6 PU/PD LVCMOS
mmc2_dat0 3 I/O
gpmc_a17 4 O
pr1_mii1_txd3 5 O
ehrpwm0_synco 6 O
gpio1_17 7 I/O
U14 GPMC_A2 gpmc_a2 0 O L L 7 VDDSHV3 Yes 6 PU/PD LVCMOS
mmc2_dat1 3 I/O
gpmc_a18 4 O
pr1_mii1_txd2 5 O
ehrpwm1A 6 O
gpio1_18 7 I/O
T14 GPMC_A3 gpmc_a3 0 O L L 7 VDDSHV3 Yes 6 PU/PD LVCMOS
mmc2_dat2 3 I/O
gpmc_a19 4 O
pr1_mii1_txd1 5 O
ehrpwm1B 6 O
gpio1_19 7 I/O
R14 GPMC_A4 gpmc_a4 0 O L L 7 VDDSHV3 Yes 6 PU/PD LVCMOS
gpmc_a20 4 O
pr1_mii1_txd0 5 O
gpio1_20 7 I/O
V15 GPMC_A5 gpmc_a5 0 O L L 7 VDDSHV3 Yes 6 PU/PD LVCMOS
gpmc_a21 4 O
pr1_mii1_rxd3 5 I
gpio1_21 7 I/O
U15 GPMC_A6 gpmc_a6 0 O L L 7 VDDSHV3 Yes 6 PU/PD LVCMOS
mmc2_dat4 3 I/O
gpmc_a22 4 O
pr1_mii1_rxd2 5 I
gpio1_22 7 I/O
T15 GPMC_A7 gpmc_a7 0 O L L 7 VDDSHV3 Yes 6 PU/PD LVCMOS
mmc2_dat5 3 I/O
gpmc_a23 4 O
pr1_mii1_rxd1 5 I
gpio1_23 7 I/O
V16 GPMC_A8 gpmc_a8 0 O L L 7 VDDSHV3 Yes 6 PU/PD LVCMOS
mmc2_dat6 3 I/O
gpmc_a24 4 O
pr1_mii1_rxd0 5 I
mcasp0_aclkx 6 I/O
gpio1_24 7 I/O
U16 GPMC_A9 (10) gpmc_a9 0 O L L 7 VDDSHV3 Yes 6 PU/PD LVCMOS
mmc2_dat7 / rmii2_crs_dv 3 I/O
gpmc_a25 4 O
pr1_mii_mr1_clk 5 I
mcasp0_fsx 6 I/O
gpio1_25 7 I/O
T16 GPMC_A10 gpmc_a10 0 O L L 7 VDDSHV3 Yes 6 PU/PD LVCMOS
gpmc_a26 4 O
pr1_mii1_rxdv 5 I
mcasp0_axr0 6 I/O
gpio1_26 7 I/O
V17 GPMC_A11 gpmc_a11 0 O L L 7 VDDSHV3 Yes 6 PU/PD LVCMOS
gpmc_a27 4 O
pr1_mii1_rxer 5 I
mcasp0_axr1 6 I/O
gpio1_27 7 I/O
U7 GPMC_AD0 gpmc_ad0 0 I/O L L 7 VDDSHV1 Yes 6 PU/PD LVCMOS
mmc1_dat0 1 I/O
gpio1_0 7 I/O
V7 GPMC_AD1 gpmc_ad1 0 I/O L L 7 VDDSHV1 Yes 6 PU/PD LVCMOS
mmc1_dat1 1 I/O
gpio1_1 7 I/O
R8 GPMC_AD2 gpmc_ad2 0 I/O L L 7 VDDSHV1 Yes 6 PU/PD LVCMOS
mmc1_dat2 1 I/O
gpio1_2 7 I/O
T8 GPMC_AD3 gpmc_ad3 0 I/O L L 7 VDDSHV1 Yes 6 PU/PD LVCMOS
mmc1_dat3 1 I/O
gpio1_3 7 I/O
U8 GPMC_AD4 gpmc_ad4 0 I/O L L 7 VDDSHV1 Yes 6 PU/PD LVCMOS
mmc1_dat4 1 I/O
gpio1_4 7 I/O
V8 GPMC_AD5 gpmc_ad5 0 I/O L L 7 VDDSHV1 Yes 6 PU/PD LVCMOS
mmc1_dat5 1 I/O
gpio1_5 7 I/O
R9 GPMC_AD6 gpmc_ad6 0 I/O L L 7 VDDSHV1 Yes 6 PU/PD LVCMOS
mmc1_dat6 1 I/O
gpio1_6 7 I/O
T9 GPMC_AD7 gpmc_ad7 0 I/O L L 7 VDDSHV1 Yes 6 PU/PD LVCMOS
mmc1_dat7 1 I/O
gpio1_7 7 I/O
U10 GPMC_AD8 gpmc_ad8 0 I/O L L 7 VDDSHV2 Yes 6 PU/PD LVCMOS
mmc1_dat0 2 I/O
mmc2_dat4 3 I/O
ehrpwm2A 4 O
pr1_mii_mt0_clk 5 I
gpio0_22 7 I/O
T10 GPMC_AD9 gpmc_ad9 0 I/O L L 7 VDDSHV2 Yes 6 PU/PD LVCMOS
mmc1_dat1 2 I/O
mmc2_dat5 3 I/O
ehrpwm2B 4 O
pr1_mii0_col 5 I
gpio0_23 7 I/O
T11 GPMC_AD10 gpmc_ad10 0 I/O L L 7 VDDSHV2 Yes 6 PU/PD LVCMOS
mmc1_dat2 2 I/O
mmc2_dat6 3 I/O
ehrpwm2_tripzone_input 4 I
pr1_mii0_txen 5 O
gpio0_26 7 I/O
U12 GPMC_AD11 gpmc_ad11 0 I/O L L 7 VDDSHV2 Yes 6 PU/PD LVCMOS
mmc1_dat3 2 I/O
mmc2_dat7 3 I/O
ehrpwm0_synco 4 O
pr1_mii0_txd3 5 O
gpio0_27 7 I/O
T12 GPMC_AD12 gpmc_ad12 0 I/O L L 7 VDDSHV2 Yes 6 PU/PD LVCMOS
mmc1_dat4 2 I/O
mmc2_dat0 3 I/O
pr1_mii0_txd2 5 O
pr1_pru0_pru_r30_14 6 O
gpio1_12 7 I/O
R12 GPMC_AD13 gpmc_ad13 0 I/O L L 7 VDDSHV2 Yes 6 PU/PD LVCMOS
mmc1_dat5 2 I/O
mmc2_dat1 3 I/O
pr1_mii0_txd1 5 O
pr1_pru0_pru_r30_15 6 O
gpio1_13 7 I/O
V13 GPMC_AD14 gpmc_ad14 0 I/O L L 7 VDDSHV2 Yes 6 PU/PD LVCMOS
mmc1_dat6 2 I/O
mmc2_dat2 3 I/O
pr1_mii0_txd0 5 O
pr1_pru0_pru_r31_14 6 I
gpio1_14 7 I/O
U13 GPMC_AD15 gpmc_ad15 0 I/O L L 7 VDDSHV2 Yes 6 PU/PD LVCMOS
mmc1_dat7 2 I/O
mmc2_dat3 3 I/O
pr1_ecap0_ecap_capin_apwm_o 5 I/O
pr1_pru0_pru_r31_15 6 I
gpio1_15 7 I/O
R7 GPMC_ADVn_ALE gpmc_advn_ale 0 O H H 7 VDDSHV1 Yes 6 PU/PD LVCMOS
timer4 2 I/O
gpio2_2 7 I/O
T6 GPMC_BEn0_CLE gpmc_be0n_cle 0 O H H 7 VDDSHV1 Yes 6 PU/PD LVCMOS
timer5 2 I/O
gpio2_5 7 I/O
U18 GPMC_BEn1 gpmc_be1n 0 O H H 7 VDDSHV3 Yes 6 PU/PD LVCMOS
gpmc_csn6 2 O
mmc2_dat3 3 I/O
gpmc_dir 4 O
pr1_mii1_rxlink 5 I
mcasp0_aclkr 6 I/O
gpio1_28 7 I/O
V12 GPMC_CLK gpmc_clk 0 I/O L L 7 VDDSHV2 Yes 6 PU/PD LVCMOS
gpmc_wait1 2 I
mmc2_clk 3 I/O
pr1_mii1_crs 4 I
pr1_mdio_mdclk 5 O
mcasp0_fsr 6 I/O
gpio2_1 7 I/O
V6 GPMC_CSn0 gpmc_csn0 0 O H H 7 VDDSHV1 Yes 6 PU/PD LVCMOS
gpio1_29 7 I/O
U9 GPMC_CSn1 gpmc_csn1 0 O H H 7 VDDSHV1 Yes 6 PU/PD LVCMOS
gpmc_clk 1 I/O
mmc1_clk 2 I/O
pr1_edio_data_in6 3 I
pr1_edio_data_out6 4 O
pr1_pru1_pru_r30_12 5 O
pr1_pru1_pru_r31_12 6 I
gpio1_30 7 I/O
V9 GPMC_CSn2 gpmc_csn2 0 O H H 7 VDDSHV1 Yes 6 PU/PD LVCMOS
gpmc_be1n 1 O
mmc1_cmd 2 I/O
pr1_edio_data_in7 3 I
pr1_edio_data_out7 4 O
pr1_pru1_pru_r30_13 5 O
pr1_pru1_pru_r31_13 6 I
gpio1_31 7 I/O
T13 GPMC_CSn3 (6) gpmc_csn3 0 O H H 7 VDDSHV2 Yes 6 PU/PD LVCMOS
gpmc_a3 1 O
mmc2_cmd 3 I/O
pr1_mii0_crs 4 I
pr1_mdio_data 5 I/O
EMU4 6 I/O
gpio2_0 7 I/O
T7 GPMC_OEn_REn gpmc_oen_ren 0 O H H 7 VDDSHV1 Yes 6 PU/PD LVCMOS
timer7 2 I/O
gpio2_3 7 I/O
T17 GPMC_WAIT0 gpmc_wait0 0 I H H 7 VDDSHV3 Yes 6 PU/PD LVCMOS
gpmc_csn4 2 O
mmc1_sdcd 4 I
pr1_mii1_col 5 I
uart4_rxd 6 I
gpio0_30 7 I/O
U6 GPMC_WEn gpmc_wen 0 O H H 7 VDDSHV1 Yes 6 PU/PD LVCMOS
timer6 2 I/O
gpio2_4 7 I/O
U17 GPMC_WPn gpmc_wpn 0 O H H 7 VDDSHV3 Yes 6 PU/PD LVCMOS
gpmc_csn5 2 O
mmc2_sdcd 4 I
pr1_mii1_txen 5 O
uart4_txd 6 O
gpio0_31 7 I/O
C17 I2C0_SDA I2C0_SDA 0 I/OD Z H 7 VDDSHV6 Yes 4 PU/PD LVCMOS
timer4 1 I/O
uart2_ctsn 2 I
eCAP2_in_PWM2_out 3 I/O
gpio3_5 7 I/O
C16 I2C0_SCL I2C0_SCL 0 I/OD Z H 7 VDDSHV6 Yes 4 PU/PD LVCMOS
timer7 1 I/O
uart2_rtsn 2 O
eCAP1_in_PWM1_out 3 I/O
gpio3_6 7 I/O
R6 LCD_AC_BIAS_EN lcd_ac_bias_en (15) 0 O Z L 7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a11 1 O
pr1_mii1_crs 2 I
pr1_edio_data_in5 3 I
pr1_edio_data_out5 4 O
pr1_pru1_pru_r30_11 5 O
pr1_pru1_pru_r31_11 6 I
gpio2_25 7 I/O
R1 LCD_DATA0 (5) lcd_data0 (15) 0 I/O Z Z 7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a0 1 O
pr1_mii_mt0_clk 2 I
ehrpwm2A 3 O
pr1_pru1_pru_r30_0 5 O
pr1_pru1_pru_r31_0 6 I
gpio2_6 7 I/O
R2 LCD_DATA1 (5) lcd_data1 (15) 0 I/O Z Z 7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a1 1 O
pr1_mii0_txen 2 O
ehrpwm2B 3 O
pr1_pru1_pru_r30_1 5 O
pr1_pru1_pru_r31_1 6 I
gpio2_7 7 I/O
R3 LCD_DATA2 (5) lcd_data2 (15) 0 I/O Z Z 7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a2 1 O
pr1_mii0_txd3 2 O
ehrpwm2_tripzone_input 3 I
pr1_pru1_pru_r30_2 5 O
pr1_pru1_pru_r31_2 6 I
gpio2_8 7 I/O
R4 LCD_DATA3 (5) lcd_data3 (15) 0 I/O Z Z 7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a3 1 O
pr1_mii0_txd2 2 O
ehrpwm0_synco 3 O
pr1_pru1_pru_r30_3 5 O
pr1_pru1_pru_r31_3 6 I
gpio2_9 7 I/O
T1 LCD_DATA4 (5) lcd_data4 (15) 0 I/O Z Z 7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a4 1 O
pr1_mii0_txd1 2 O
pr1_pru1_pru_r30_4 5 O
pr1_pru1_pru_r31_4 6 I
gpio2_10 7 I/O
T2 LCD_DATA5 (5) lcd_data5 (15) 0 I/O Z Z 7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a5 1 O
pr1_mii0_txd0 2 O
pr1_pru1_pru_r30_5 5 O
pr1_pru1_pru_r31_5 6 I
gpio2_11 7 I/O
T3 LCD_DATA6 (5) lcd_data6 (15) 0 I/O Z Z 7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a6 1 O
pr1_edio_data_in6 2 I
pr1_edio_data_out6 4 O
pr1_pru1_pru_r30_6 5 O
pr1_pru1_pru_r31_6 6 I
gpio2_12 7 I/O
T4 LCD_DATA7 (5) lcd_data7 (15) 0 I/O Z Z 7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a7 1 O
pr1_edio_data_in7 2 I
pr1_edio_data_out7 4 O
pr1_pru1_pru_r30_7 5 O
pr1_pru1_pru_r31_7 6 I
gpio2_13 7 I/O
U1 LCD_DATA8 (5) lcd_data8 (15) 0 I/O Z Z 7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a12 1 O
ehrpwm1_tripzone_input 2 I
mcasp0_aclkx 3 I/O
uart5_txd 4 O
pr1_mii0_rxd3 5 I
uart2_ctsn 6 I
gpio2_14 7 I/O
U2 LCD_DATA9 (5) lcd_data9 (15) 0 I/O Z Z 7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a13 1 O
ehrpwm0_synco 2 O
mcasp0_fsx 3 I/O
uart5_rxd 4 I
pr1_mii0_rxd2 5 I
uart2_rtsn 6 O
gpio2_15 7 I/O
U3 LCD_DATA10 (5) lcd_data10 (15) 0 I/O Z Z 7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a14 1 O
ehrpwm1A 2 O
mcasp0_axr0 3 I/O
pr1_mii0_rxd1 5 I
uart3_ctsn 6 I
gpio2_16 7 I/O
U4 LCD_DATA11 (5) lcd_data11 (15) 0 I/O Z Z 7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a15 1 O
ehrpwm1B 2 O
mcasp0_ahclkr 3 I/O
mcasp0_axr2 4 I/O
pr1_mii0_rxd0 5 I
uart3_rtsn 6 O
gpio2_17 7 I/O
V2 LCD_DATA12 (5) lcd_data12 (15) 0 I/O Z Z 7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a16 1 O
mcasp0_aclkr 3 I/O
mcasp0_axr2 4 I/O
pr1_mii0_rxlink 5 I
uart4_ctsn 6 I
gpio0_8 7 I/O
V3 LCD_DATA13 (5) lcd_data13 (15) 0 I/O Z Z 7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a17 1 O
mcasp0_fsr 3 I/O
mcasp0_axr3 4 I/O
pr1_mii0_rxer 5 I
uart4_rtsn 6 O
gpio0_9 7 I/O
V4 LCD_DATA14 (5) lcd_data14 (15) 0 I/O Z Z 7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a18 1 O
mcasp0_axr1 3 I/O
uart5_rxd 4 I
pr1_mii_mr0_clk 5 I
uart5_ctsn 6 I
gpio0_10 7 I/O
T5 LCD_DATA15 (5) lcd_data15 (15) 0 I/O Z Z 7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a19 1 O
mcasp0_ahclkx 3 I/O
mcasp0_axr3 4 I/O
pr1_mii0_rxdv 5 I
uart5_rtsn 6 O
gpio0_11 7 I/O
R5 LCD_HSYNC (7) lcd_hsync (15) 0 O Z L 7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a9 1 O
gpmc_a2 2 O
pr1_edio_data_in3 3 I
pr1_edio_data_out3 4 O
pr1_pru1_pru_r30_9 5 O
pr1_pru1_pru_r31_9 6 I
gpio2_23 7 I/O
V5 LCD_PCLK lcd_pclk (15) 0 O Z L 7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a10 1 O
pr1_mii0_crs 2 I
pr1_edio_data_in4 3 I
pr1_edio_data_out4 4 O
pr1_pru1_pru_r30_10 5 O
pr1_pru1_pru_r31_10 6 I
gpio2_24 7 I/O
U5 LCD_VSYNC (7) lcd_vsync (15) 0 O Z L 7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a8 1 O
gpmc_a1 2 O
pr1_edio_data_in2 3 I
pr1_edio_data_out2 4 O
pr1_pru1_pru_r30_8 5 O
pr1_pru1_pru_r31_8 6 I
gpio2_22 7 I/O
B13 MCASP0_FSX mcasp0_fsx 0 I/O L L 7 VDDSHV6 Yes 6 PU/PD LVCMOS
ehrpwm0B 1 O
spi1_d0 3 I/O
mmc1_sdcd 4 I
pr1_pru0_pru_r30_1 5 O
pr1_pru0_pru_r31_1 6 I
gpio3_15 7 I/O
B12 MCASP0_ACLKR mcasp0_aclkr 0 I/O L L 7 VDDSHV6 Yes 6 PU/PD LVCMOS
mcasp0_axr2 2 I/O
mcasp1_aclkx 3 I/O
mmc0_sdwp 4 I
pr1_pru0_pru_r30_4 5 O
pr1_pru0_pru_r31_4 6 I
gpio3_18 7 I/O
C12 MCASP0_AHCLKR mcasp0_ahclkr 0 I/O L L 7 VDDSHV6 Yes 6 PU/PD LVCMOS
ehrpwm0_synci 1 I
mcasp0_axr2 2 I/O
spi1_cs0 3 I/O
eCAP2_in_PWM2_out 4 I/O
pr1_pru0_pru_r30_3 5 O
pr1_pru0_pru_r31_3 6 I
gpio3_17 7 I/O
A14 MCASP0_AHCLKX mcasp0_ahclkx 0 I/O L L 7 VDDSHV6 Yes 6 PU/PD LVCMOS
mcasp0_axr3 2 I/O
mcasp1_axr1 3 I/O
EMU4 4 I/O
pr1_pru0_pru_r30_7 5 O
pr1_pru0_pru_r31_7 6 I
gpio3_21 7 I/O
A13 MCASP0_ACLKX mcasp0_aclkx 0 I/O L L 7 VDDSHV6 Yes 6 PU/PD LVCMOS
ehrpwm0A 1 O
spi1_sclk 3 I/O
mmc0_sdcd 4 I
pr1_pru0_pru_r30_0 5 O
pr1_pru0_pru_r31_0 6 I
gpio3_14 7 I/O
C13 MCASP0_FSR mcasp0_fsr 0 I/O L L 7 VDDSHV6 Yes 6 PU/PD LVCMOS
mcasp0_axr3 2 I/O
mcasp1_fsx 3 I/O
EMU2 4 I/O
pr1_pru0_pru_r30_5 5 O
pr1_pru0_pru_r31_5 6 I
gpio3_19 7 I/O
D12 MCASP0_AXR0 mcasp0_axr0 0 I/O L L 7 VDDSHV6 Yes 6 PU/PD LVCMOS
ehrpwm0_tripzone_input 1 I
spi1_d1 3 I/O
mmc2_sdcd 4 I
pr1_pru0_pru_r30_2 5 O
pr1_pru0_pru_r31_2 6 I
gpio3_16 7 I/O
D13 MCASP0_AXR1 mcasp0_axr1 0 I/O L L 7 VDDSHV6 Yes 6 PU/PD LVCMOS
mcasp1_axr0 3 I/O
EMU3 4 I/O
pr1_pru0_pru_r30_6 5 O
pr1_pru0_pru_r31_6 6 I
gpio3_20 7 I/O
M18 MDC mdio_clk 0 O H H 7 VDDSHV5 Yes 6 PU/PD LVCMOS
timer5 1 I/O
uart5_txd 2 O
uart3_rtsn 3 O
mmc0_sdwp 4 I
mmc1_clk 5 I/O
mmc2_clk 6 I/O
gpio0_1 7 I/O
M17 MDIO mdio_data 0 I/O H H 7 VDDSHV5 Yes 6 PU/PD LVCMOS
timer6 1 I/O
uart5_rxd 2 I
uart3_ctsn 3 I
mmc0_sdcd 4 I
mmc1_cmd 5 I/O
mmc2_cmd 6 I/O
gpio0_0 7 I/O
J17 MII1_RX_DV gmii1_rxdv 0 I L L 7 VDDSHV5 Yes 6 PU/PD LVCMOS
rgmii1_rctl 2 I
uart5_txd 3 O
mcasp1_aclkx 4 I/O
mmc2_dat0 5 I/O
mcasp0_aclkr 6 I/O
gpio3_4 7 I/O
J16 MII1_TX_EN gmii1_txen 0 O L L 7 VDDSHV5 Yes 6 PU/PD LVCMOS
rmii1_txen 1 I
rgmii1_tctl 2 I
timer4 3 I/O
mcasp1_axr0 4 I/O
mmc2_cmd 6 I/O
gpio3_3 7 I/O
J15 MII1_RX_ER gmii1_rxerr 0 I L L 7 VDDSHV5 Yes 6 PU/PD LVCMOS
rmii1_rxerr 1 I
spi1_d1 2 I/O
I2C1_SCL 3 I/OD
mcasp1_fsx 4 I/O
uart5_rtsn 5 O
uart2_txd 6 O
gpio3_2 7 I/O
L18 MII1_RX_CLK gmii1_rxclk 0 I L L 7 VDDSHV5 Yes 6 PU/PD LVCMOS
uart2_txd 1 O
rgmii1_rclk 2 I
mmc0_dat6 3 I/O
mmc1_dat1 4 I/O
uart1_dsrn 5 I
mcasp0_fsx 6 I/O
gpio3_10 7 I/O
K18 MII1_TX_CLK gmii1_txclk 0 I L L 7 VDDSHV5 Yes 6 PU/PD LVCMOS
uart2_rxd 1 I
rgmii1_rclk 2 I
mmc0_dat7 3 I/O
mmc1_dat0 4 I/O
uart1_dcdn 5 I
mcasp0_aclkx 6 I/O
gpio3_9 7 I/O
H16 MII1_COL gmii1_col 0 I L L 7 VDDSHV5 Yes 6 PU/PD LVCMOS
spi1_sclk 2 I/O
uart5_rxd 3 I
mcasp1_axr2 4 I/O
mmc2_dat3 5 I/O
mcasp0_axr2 6 I/O
gpio3_0 7 I/O
H17 MII1_CRS gmii1_crs 0 I L L 7 VDDSHV5 Yes 6 PU/PD LVCMOS
rmii1_crs_dv 1 I
spi1_d0 2 I/O
I2C1_SDA 3 I/OD
mcasp1_aclkx 4 I/O
uart5_ctsn 5 I
uart2_rxd 6 I
gpio3_1 7 I/O
M16 MII1_RXD0 gmii1_rxd0 0 I L L 7 VDDSHV5 Yes 6 PU/PD LVCMOS
rmii1_rxd0 1 I
rgmii1_rd0 2 I
mcasp1_ahclkx 3 I/O
mcasp1_ahclkr 4 I/O
mcasp1_aclkr 5 I/O
mcasp0_axr3 6 I/O
gpio2_21 7 I/O
L15 MII1_RXD1 gmii1_rxd1 0 I L L 7 VDDSHV5 Yes 6 PU/PD LVCMOS
rmii1_rxd1 1 I
rgmii1_rd1 2 I
mcasp1_axr3 3 I/O
mcasp1_fsr 4 I/O
mmc2_clk 6 I/O
gpio2_20 7 I/O
L16 MII1_RXD2 gmii1_rxd2 0 I L L 7 VDDSHV5 Yes 6 PU/PD LVCMOS
uart3_txd 1 O
rgmii1_rd2 2 I
mmc0_dat4 3 I/O
mmc1_dat3 4 I/O
uart1_rin 5 I
mcasp0_axr1 6 I/O
gpio2_19 7 I/O
L17 MII1_RXD3 gmii1_rxd3 0 I L L 7 VDDSHV5 Yes 6 PU/PD LVCMOS
uart3_rxd 1 I
rgmii1_rd3 2 I
mmc0_dat5 3 I/O
mmc1_dat2 4 I/O
uart1_dtrn 5 O
mcasp0_axr0 6 I/O
gpio2_18 7 I/O
K17 MII1_TXD0 gmii1_txd0 0 O L L 7 VDDSHV5 Yes 6 PU/PD LVCMOS
rmii1_txd0 1 I
rgmii1_td0 2 I
mcasp1_axr2 3 I/O
mcasp1_aclkr 4 I/O
mmc1_clk 6 I/O
gpio0_28 7 I/O
K16 MII1_TXD1 gmii1_txd1 0 O L L 7 VDDSHV5 Yes 6 PU/PD LVCMOS
rmii1_txd1 1 I
rgmii1_td1 2 I
mcasp1_fsr 3 I/O
mcasp1_axr1 4 I/O
mmc1_cmd 6 I/O
gpio0_21 7 I/O
K15 MII1_TXD2 gmii1_txd2 0 O L L 7 VDDSHV5 Yes 6 PU/PD LVCMOS
dcan0_rx 1 I
rgmii1_td2 2 I
uart4_txd 3 O
mcasp1_axr0 4 I/O
mmc2_dat2 5 I/O
mcasp0_ahclkx 6 I/O
gpio0_17 7 I/O
J18 MII1_TXD3 gmii1_txd3 0 O L L 7 VDDSHV5 Yes 6 PU/PD LVCMOS
dcan0_tx 1 O
rgmii1_td3 2 I
uart4_rxd 3 I
mcasp1_fsx 4 I/O
mmc2_dat1 5 I/O
mcasp0_fsr 6 I/O
gpio0_16 7 I/O
G18 MMC0_CMD mmc0_cmd 0 I/O H H 7 VDDSHV4 Yes 6 PU/PD LVCMOS
gpmc_a25 1 O
uart3_rtsn 2 O
uart2_txd 3 O
dcan1_rx 4 I
pr1_pru0_pru_r30_13 5 O
pr1_pru0_pru_r31_13 6 I
gpio2_31 7 I/O
G17 MMC0_CLK mmc0_clk 0 I/O H H 7 VDDSHV4 Yes 6 PU/PD LVCMOS
gpmc_a24 1 O
uart3_ctsn 2 I
uart2_rxd 3 I
dcan1_tx 4 O
pr1_pru0_pru_r30_12 5 O
pr1_pru0_pru_r31_12 6 I
gpio2_30 7 I/O
G16 MMC0_DAT0 mmc0_dat0 0 I/O H H 7 VDDSHV4 Yes 6 PU/PD LVCMOS
gpmc_a23 1 O
uart5_rtsn 2 O
uart3_txd 3 O
uart1_rin 4 I
pr1_pru0_pru_r30_11 5 O
pr1_pru0_pru_r31_11 6 I
gpio2_29 7 I/O
G15 MMC0_DAT1 mmc0_dat1 0 I/O H H 7 VDDSHV4 Yes 6 PU/PD LVCMOS
gpmc_a22 1 O
uart5_ctsn 2 I
uart3_rxd 3 I
uart1_dtrn 4 O
pr1_pru0_pru_r30_10 5 O
pr1_pru0_pru_r31_10 6 I
gpio2_28 7 I/O
F18 MMC0_DAT2 mmc0_dat2 0 I/O H H 7 VDDSHV4 Yes 6 PU/PD LVCMOS
gpmc_a21 1 O
uart4_rtsn 2 O
timer6 3 I/O
uart1_dsrn 4 I
pr1_pru0_pru_r30_9 5 O
pr1_pru0_pru_r31_9 6 I
gpio2_27 7 I/O
F17 MMC0_DAT3 mmc0_dat3 0 I/O H H 7 VDDSHV4 Yes 6 PU/PD LVCMOS
gpmc_a20 1 O
uart4_ctsn 2 I
timer5 3 I/O
uart1_dcdn 4 I
pr1_pru0_pru_r30_8 5 O
pr1_pru0_pru_r31_8 6 I
gpio2_26 7 I/O
C6 PMIC_POWER_EN PMIC_POWER_EN 0 O H 1 0 VDDS_RTC NA 6 NA LVCMOS
B15 PWRONRSTn porz 0 I Z Z 0 VDDSHV6 (12) Yes NA NA LVCMOS
A3 RESERVED (3) testout 0 O NA NA NA VDDSHV6 NA NA NA Analog
H18 RMII1_REF_CLK rmii1_refclk 0 I/O L L 7 VDDSHV5 Yes 6 PU/PD LVCMOS
xdma_event_intr2 1 I
spi1_cs0 2 I/O
uart5_txd 3 O
mcasp1_axr3 4 I/O
mmc0_pow 5 O
mcasp1_ahclkx 6 I/O
gpio0_29 7 I/O
B4 RTC_KALDO_ENn ENZ_KALDO_1P8V 0 I Z Z 0 VDDS_RTC NA NA NA Analog
B5 RTC_PWRONRSTn RTC_PORz 0 I Z Z 0 VDDS_RTC Yes NA NA LVCMOS
A6 RTC_XTALIN OSC1_IN 0 I H H 0 VDDS_RTC Yes NA PU (1) LVCMOS
A4 RTC_XTALOUT OSC1_OUT 0 O Z (24) Z (24) 0 VDDS_RTC NA NA (16) NA LVCMOS
A17 SPI0_SCLK spi0_sclk 0 I/O Z H 7 VDDSHV6 Yes 6 PU/PD LVCMOS
uart2_rxd 1 I
I2C2_SDA 2 I/OD
ehrpwm0A 3 O
pr1_uart0_cts_n 4 I
pr1_edio_sof 5 O
EMU2 6 I/O
gpio0_2 7 I/O
A16 SPI0_CS0 spi0_cs0 0 I/O Z H 7 VDDSHV6 Yes 6 PU/PD LVCMOS
mmc2_sdwp 1 I
I2C1_SCL 2 I/OD
ehrpwm0_synci 3 I
pr1_uart0_txd 4 O
pr1_edio_data_in1 5 I
pr1_edio_data_out1 6 O
gpio0_5 7 I/O
C15 SPI0_CS1 spi0_cs1 0 I/O Z H 7 VDDSHV6 Yes 6 PU/PD LVCMOS
uart3_rxd 1 I
eCAP1_in_PWM1_out 2 I/O
mmc0_pow 3 O
xdma_event_intr2 4 I
mmc0_sdcd 5 I
EMU4 6 I/O
gpio0_6 7 I/O
B17 SPI0_D0 spi0_d0 0 I/O Z H 7 VDDSHV6 Yes 6 PU/PD LVCMOS
uart2_txd 1 O
I2C2_SCL 2 I/OD
ehrpwm0B 3 O
pr1_uart0_rts_n 4 O
pr1_edio_latch_in 5 I
EMU3 6 I/O
gpio0_3 7 I/O
B16 SPI0_D1 spi0_d1 0 I/O Z H 7 VDDSHV6 Yes 6 PU/PD LVCMOS
mmc1_sdwp 1 I
I2C1_SDA 2 I/OD
ehrpwm0_tripzone_input 3 I
pr1_uart0_rxd 4 I
pr1_edio_data_in0 5 I
pr1_edio_data_out0 6 O
gpio0_4 7 I/O
A12 TCK TCK 0 I H H 0 VDDSHV6 Yes NA PU/PD LVCMOS
B11 TDI TDI 0 I H H 0 VDDSHV6 Yes NA PU/PD LVCMOS
A11 TDO TDO 0 O H H 0 VDDSHV6 NA 4 PU/PD LVCMOS
C11 TMS TMS 0 I H H 0 VDDSHV6 Yes NA PU/PD LVCMOS
B10 TRSTn nTRST 0 I L L 0 VDDSHV6 Yes NA PU/PD LVCMOS
E16 UART0_TXD uart0_txd 0 O Z H 7 VDDSHV6 Yes 4 PU/PD LVCMOS
spi1_cs1 1 I/O
dcan0_rx 2 I
I2C2_SCL 3 I/OD
eCAP1_in_PWM1_out 4 I/O
pr1_pru1_pru_r30_15 5 O
pr1_pru1_pru_r31_15 6 I
gpio1_11 7 I/O
E18 UART0_CTSn uart0_ctsn 0 I Z H 7 VDDSHV6 Yes 4 PU/PD LVCMOS
uart4_rxd 1 I
dcan1_tx 2 O
I2C1_SDA 3 I/OD
spi1_d0 4 I/O
timer7 5 I/O
pr1_edc_sync0_out 6 O
gpio1_8 7 I/O
E15 UART0_RXD uart0_rxd 0 I Z H 7 VDDSHV6 Yes 4 PU/PD LVCMOS
spi1_cs0 1 I/O
dcan0_tx 2 O
I2C2_SDA 3 I/OD
eCAP2_in_PWM2_out 4 I/O
pr1_pru1_pru_r30_14 5 O
pr1_pru1_pru_r31_14 6 I
gpio1_10 7 I/O
E17 UART0_RTSn uart0_rtsn 0 O Z H 7 VDDSHV6 Yes 4 PU/PD LVCMOS
uart4_txd 1 O
dcan1_rx 2 I
I2C1_SCL 3 I/OD
spi1_d1 4 I/O
spi1_cs0 5 I/O
pr1_edc_sync1_out 6 O
gpio1_9 7 I/O
D15 UART1_TXD uart1_txd 0 O Z H 7 VDDSHV6 Yes 4 PU/PD LVCMOS
mmc2_sdwp 1 I
dcan1_rx 2 I
I2C1_SCL 3 I/OD
pr1_uart0_txd 5 O
pr1_pru0_pru_r31_16 6 I
gpio0_15 7 I/O
D16 UART1_RXD uart1_rxd 0 I Z H 7 VDDSHV6 Yes 4 PU/PD LVCMOS
mmc1_sdwp 1 I
dcan1_tx 2 O
I2C1_SDA 3 I/OD
pr1_uart0_rxd 5 I
pr1_pru1_pru_r31_16 6 I
gpio0_14 7 I/O
D17 UART1_RTSn uart1_rtsn 0 O Z H 7 VDDSHV6 Yes 4 PU/PD LVCMOS
timer5 1 I/O
dcan0_rx 2 I
I2C2_SCL 3 I/OD
spi1_cs1 4 I/O
pr1_uart0_rts_n 5 O
pr1_edc_latch1_in 6 I
gpio0_13 7 I/O
D18 UART1_CTSn uart1_ctsn 0 I Z H 7 VDDSHV6 Yes 4 PU/PD LVCMOS
timer6 1 I/O
dcan0_tx 2 O
I2C2_SDA 3 I/OD
spi1_cs0 4 I/O
pr1_uart0_cts_n 5 I
pr1_edc_latch0_in 6 I
gpio0_12 7 I/O
M15 USB0_CE USB0_CE 0 A Z Z 0 VDDA*_USB0 (27) NA NA NA Analog
P15 USB0_VBUS USB0_VBUS 0 A Z Z 0 VDDA*_USB0 (27) NA NA NA Analog
N18 USB0_DM USB0_DM 0 A Z Z 0 (13) VDDA*_USB0 (27) Yes (17) 8 (17) NA Analog
F16 USB0_DRVVBUS USB0_DRVVBUS 0 O L 0(PD) 0 VDDSHV6 Yes 4 PU/PD LVCMOS
gpio0_18 7 I/O
P16 USB0_ID USB0_ID 0 A Z Z 0 VDDA*_USB0 (27) NA NA NA Analog
N17 USB0_DP USB0_DP 0 A Z Z 0 (13) VDDA*_USB0 (27) Yes (17) 8 (17) NA Analog
P18 USB1_CE USB1_CE 0 A Z Z 0 VDDA*_USB1 (28) NA NA NA Analog
P17 USB1_ID USB1_ID 0 A Z Z 0 VDDA*_USB1 (28) NA NA NA Analog
T18 USB1_VBUS USB1_VBUS 0 A Z Z 0 VDDA*_USB1 (28) NA NA NA Analog
R17 USB1_DP USB1_DP 0 A Z Z 0 (14) VDDA*_USB1 (28) Yes (18) 8 (18) NA Analog
F15 USB1_DRVVBUS USB1_DRVVBUS 0 O L 0(PD) 0 VDDSHV6 Yes 4 PU/PD LVCMOS
gpio3_13 7 I/O
R18 USB1_DM USB1_DM 0 A Z Z 0 (14) VDDA*_USB1 (28) Yes (18) 8 (18) NA Analog
N16 VDDA1P8V_USB0 VDDA1P8V_USB0 NA PWR
R16 VDDA1P8V_USB1 VDDA1P8V_USB1 NA PWR
N15 VDDA3P3V_USB0 VDDA3P3V_USB0 NA PWR
R15 VDDA3P3V_USB1 VDDA3P3V_USB1 NA PWR
D8 VDDA_ADC VDDA_ADC NA PWR
E6, E14, F9, K13, N6, P9, P14 VDDS VDDS NA PWR
P7, P8 VDDSHV1 VDDSHV1 NA PWR
P10, P11 VDDSHV2 VDDSHV2 NA PWR
P12, P13 VDDSHV3 VDDSHV3 NA PWR
H14, J14 VDDSHV4 VDDSHV4 NA PWR
K14, L14 VDDSHV5 VDDSHV5 NA PWR
E10, E11, E12, E13, F14, G14, N5, P5, P6 VDDSHV6 VDDSHV6 NA PWR
E5, F5, G5, H5, J5, K5, L5 VDDS_DDR VDDS_DDR NA PWR
R11 VDDS_OSC VDDS_OSC NA PWR
R10 VDDS_PLL_CORE_LCD VDDS_PLL_CORE_LCD NA PWR
E7 VDDS_PLL_DDR VDDS_PLL_DDR NA PWR
H15 VDDS_PLL_MPU VDDS_PLL_MPU NA PWR
D7 VDDS_RTC VDDS_RTC NA PWR
E9 VDDS_SRAM_CORE_BG VDDS_SRAM_CORE_BG NA PWR
D10 VDDS_SRAM_MPU_BB VDDS_SRAM_MPU_BB NA PWR
F6, F7, G6, G7, G10, H11, J12, K6, K8, K12, L6, L7, L8, L9, M11, M13, N8, N9, N12, N13 VDD_CORE VDD_CORE NA PWR
F10, F11, F12, F13, G13, H13, J13 VDD_MPU VDD_MPU NA PWR
A2 VDD_MPU_MON VDD_MPU_MON (31) NA A
M5 VPP VPP NA PWR
A9 VREFN VREFN 0 AP Z Z 0 VDDA_ADC NA NA NA Analog
B9 VREFP VREFP 0 AP Z Z 0 VDDA_ADC NA NA NA Analog
A1, A18, F8, G8, G9, G11, G12, H6, H7, H8, H9, H10, H12, J6, J7, J8, J9, J10, J11, K7, K9, K10, K11, L10, L11, L12, L13, M6, M7, M8, M9, M10, M12, N7, N10, N11, V1, V18 VSS VSS NA GND
E8 VSSA_ADC VSSA_ADC NA GND
M14, N14 VSSA_USB VSSA_USB NA GND
V11 VSS_OSC VSS_OSC (29) NA A
A5 VSS_RTC VSS_RTC (30) NA A
A10 WARMRSTn nRESETIN_OUT 0 I/OD (8) 0 (26) 0(PU) (11) 0 VDDSHV6 Yes 4 PU/PD LVCMOS
A15 XDMA_EVENT_INTR0 xdma_event_intr0 0 I Z (4) (9) VDDSHV6 Yes 4 PU/PD LVCMOS
timer4 2 I/O
clkout1 3 O
spi1_cs1 4 I/O
pr1_pru1_pru_r31_16 5 I
EMU2 6 I/O
gpio0_19 7 I/O
D14 XDMA_EVENT_INTR1 xdma_event_intr1 0 I Z L 7 VDDSHV6 Yes 4 PU/PD LVCMOS
tclkin 2 I
clkout2 3 O
timer7 4 I/O
pr1_pru0_pru_r31_16 5 I
EMU3 6 I/O
gpio0_20 7 I/O
V10 XTALIN OSC0_IN 0 I Z Z 0 VDDS_OSC Yes NA PD (2) LVCMOS
U11 XTALOUT OSC0_OUT 0 O (25) (25) 0 VDDS_OSC NA NA (16) NA LVCMOS
  1. An internal 10 kohm pull up is turned on when the oscillator is diasabled. The oscillator is disabled by default after power is applied.
  2. An internal 15 kohm pull down is turned on when the oscillator is disabled. The oscillator is enabled by default after power is applied.
  3. Do not connect anything to this terminal.
  4. If sysboot[5] is low on the rising edge of PWRONRSTn, this terminal has an internal pull-down turned on after reset is released. If sysboot[5] is high on the rising edge or PWRONRSTn, this terminal will initially be driven low after reset is released then it begins to toggle at the same frequency of the XTALIN terminal.
  5. LCD_DATA[15:0] terminals are respectively SYSBOOT[15:0] inputs, latched on the rising edge of PWRONRSTn.
  6. Mode1 and Mode2 signal assignments for this terminal are only available with silicon revision 2.0 or newer devices.
  7. Mode2 signal assignment for this terminal is only available with silicon revision 2.0 or newer devices.
  8. Refer to the External Warm Reset section of the AM335x and AMIC110 Sitara Processors Technical Reference Manual for more information related to the operation of this terminal.
  9. Reset Release Mode = 7 if sysboot[5] is low. Mode = 3 if sysboot[5] is high.
  10. Silicon revision 1.0 devices only provide the MMC2_DAT7 signal when Mode3 is selected. Silicon revision 2.0 and newer devices implement another level of pin multiplexing which provides the original MMC2_DAT7 signal or RMII2_CRS_DV signal when Mode3 is selected. This new level of pin multiplexing is selected with bit zero of the SMA2 register. For more details refer to the Control Module section of the AM335x and AMIC110 Sitara Processors Technical Reference Manual.
  11. The 0(PU) indicates that this terminal is initially low based on the description in the AM335x and AMIC110 Sitara Processors Technical Reference Manual. However, it is also has a weak internal pull up applied.
  12. The input voltage thresholds for this input are not a function of VDDSHV6. Please refer to the DC Electrical Characteristics section for details related to electrical parameters associated with this input terminal.
  13. The internal USB PHY can be configured to multiplex the UART2_TX or UART2_RX signals to this terminal. For more details refer to USB GPIO Details section of the AM335x and AMIC110 Sitara Processors Technical Reference Manual.
  14. The internal USB PHY can be configured to multiplex the UART3_TX or UART3_RX signals to this terminal. For more details refer to USB GPIO Details section of the AM335x and AMIC110 Sitara Processors Technical Reference Manual.
  15. This function is not available on this device, but signal names are retained for consistency with the AM335x family of devices.
  16. This output should only be used to source the recommended crystal circuit.
  17. This parameter only applies when this USB PHY terminal is operating in UART2 mode.
  18. This parameter only applies when this USB PHY terminal is operating in UART3 mode.
  19. This terminal is a analog input used to set the switching threshold of the DDR input buffers to (VDDS_DDR / 2).
  20. This terminal is a analog passive signal that connects to an external 49.9 ohm 1%, 20mW reference resistor which is used to calibrate the DDR input/output buffers.
  21. This terminal is analog input that may also be configured as an open-drain output.
  22. This terminal is analog input that may also be configured as an open-source or open-drain output.
  23. This terminal is analog input that may also be configured as an open-source output.
  24. This terminal is high-Z when the oscillator is diasabled. This terminal is driven high if RTC_XTALIN is less than VIL, driven low if RTC_XTALIN is greater than VIH, and driven to a unknown value if RTC_XTALIN is between VIL and VIH when the oscillator is enabled. The oscillator is disabled by default after power is applied.
  25. This terminal is high-Z when the oscillator is diasabled. This terminal is driven high if XTALIN is less than VIL, driven low if XTALIN is greater than VIH, and driven to a unknown value if XTALIN is between VIL and VIH when the oscillator is enabled. The oscillator is enabled by default after power is applied.
  26. This terminal is not defined until all the supplies are ramped.
  27. This terminal requires two power supplies, VDDA3p3v_USB0 and VDDA1p8v_USB0. The "*" character in the power supply name is a wild card that represents "3p3v" and "1p8v".
  28. This terminal requires two power supplies, VDDA3p3v_USB1 and VDDA1p8v_USB1. The "*" character in the power supply name is a wild card that represents "3p3v" and "1p8v".
  29. Refer to Section 6.2.2 for additional details about VSS_OSC.
  30. Refer to Section 6.2.2 for additional details about VSS_RTC.
  31. This terminal provides a Kelvin connection to VDD_MPU. It can be connected to the power supply feedback input to provide remote sensing which compensates for voltage drop in the PCB power distribution network and package. When the Kelvin connection is not used it should be connected to the same power source as VDD_MPU.