SPRSP09B December   2017  – January 2019 AMIC120

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
      1. Table 4-1 ZDN Ball Map [Section Top Left - Top View]
      2. Table 4-2 ZDN Ball Map [Section Top Middle - Top View]
      3. Table 4-3 ZDN Ball Map [Section Top Right - Top View]
      4. Table 4-4 ZDN Ball Map [Section Middle Left - Top View]
      5. Table 4-5 ZDN Ball Map [Section Middle Middle - Top View]
      6. Table 4-6 ZDN Ball Map [Section Middle Right - Top View]
      7. Table 4-7 ZDN Ball Map [Section Bottom Left - Top View]
      8. Table 4-8 ZDN Ball Map [Section Bottom Middle - Top View]
      9. Table 4-9 ZDN Ball Map [Section Bottom Right - Top View]
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  ADC Interfaces
      2. 4.3.2  CAN Interfaces
      3. 4.3.3  Debug Subsystem Interface
      4. 4.3.4  Ethernet (GEMAC_CPSW) Interfaces
      5. 4.3.5  External Memory Interfaces
      6. 4.3.6  General Purpose IOs
      7. 4.3.7  HDQ Interface
      8. 4.3.8  I2C Interfaces
      9. 4.3.9  McASP Interfaces
      10. 4.3.10 Miscellaneous
      11. 4.3.11 PRU-ICSS0 Interface
      12. 4.3.12 PRU-ICSS1 Interface
      13. 4.3.13 QSPI Interface
      14. 4.3.14 RTC Subsystem Interface
      15. 4.3.15 Removable Media Interfaces
      16. 4.3.16 SPI Interfaces
      17. 4.3.17 Timer Interfaces
      18. 4.3.18 UART Interfaces
      19. 4.3.19 USB Interfaces
      20. 4.3.20 eCAP Interfaces
      21. 4.3.21 eHRPWM Interfaces
      22. 4.3.22 eQEP Interfaces
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Operating Performance Points
    5. 5.5  Recommended Operating Conditions
    6. 5.6  Power Consumption Summary
    7. 5.7  DC Electrical Characteristics
    8. 5.8  ADC0: Analog-to-Digital Subsystem Electrical Parameters
    9. 5.9  Thermal Resistance Characteristics
      1. Table 5-6 Thermal Resistance Characteristics (NFBGA Package) [ZDN]
    10. 5.10 External Capacitors
      1. 5.10.1 Voltage Decoupling Capacitors
        1. 5.10.1.1 Core Voltage Decoupling Capacitors
        2. 5.10.1.2 IO and Analog Voltage Decoupling Capacitors
      2. 5.10.2 Output Capacitors
    11. 5.11 Timing and Switching Characteristics
      1. 5.11.1  Power Supply Sequencing
        1. 5.11.1.1 Power Supply Slew Rate Requirement
        2. 5.11.1.2 Power-Up Sequencing
        3. 5.11.1.3 Power-Down Sequencing
      2. 5.11.2  Clock
        1. 5.11.2.1 PLLs
          1. 5.11.2.1.1 Digital Phase-Locked Loop Power Supply Requirements
        2. 5.11.2.2 Input Clock Specifications
        3. 5.11.2.3 Input Clock Requirements
          1. 5.11.2.3.1 OSC0 Internal Oscillator Clock Source
            1. Table 5-11 OSC0 Crystal Circuit Requirements
            2. Table 5-12 OSC0 Crystal Circuit Characteristics
          2. 5.11.2.3.2 OSC0 LVCMOS Digital Clock Source
          3. 5.11.2.3.3 OSC1 Internal Oscillator Clock Source
            1. Table 5-14 OSC1 Crystal Circuit Requirements
            2. Table 5-15 OSC1 Crystal Circuit Characteristics
          4. 5.11.2.3.4 OSC1 LVCMOS Digital Clock Source
          5. 5.11.2.3.5 OSC1 Not Used
        4. 5.11.2.4 Output Clock Specifications
        5. 5.11.2.5 Output Clock Characteristics
          1. 5.11.2.5.1 CLKOUT1
          2. 5.11.2.5.2 CLKOUT2
      3. 5.11.3  Timing Parameters and Board Routing Analysis
      4. 5.11.4  Recommended Clock and Control Signal Transition Behavior
      5. 5.11.5  Controller Area Network (CAN)
        1. 5.11.5.1 DCAN Electrical Data and Timing
          1. Table 5-17 Timing Requirements for DCANx Receive
          2. Table 5-18 Switching Characteristics for DCANx Transmit
      6. 5.11.6  DMTimer
        1. 5.11.6.1 DMTimer Electrical Data and Timing
          1. Table 5-19 Timing Requirements for DMTimer [1-11]
          2. Table 5-20 Switching Characteristics for DMTimer [4-7]
      7. 5.11.7  Ethernet Media Access Controller (EMAC) and Switch
        1. 5.11.7.1 Ethernet MAC and Switch Electrical Data and Timing
          1. Table 5-21 Ethernet MAC and Switch Timing Conditions
          2. 5.11.7.1.1 Ethernet MAC/Switch MDIO Electrical Data and Timing
            1. Table 5-22 Timing Requirements for MDIO_DATA
            2. Table 5-23 Switching Characteristics for MDIO_CLK
            3. Table 5-24 MDIO Switching Characteristics - MDIO_DATA
          3. 5.11.7.1.2 Ethernet MAC and Switch MII Electrical Data and Timing
            1. Table 5-25 Timing Requirements for GMII[x]_RXCLK - MII Mode
            2. Table 5-26 Timing Requirements for GMII[x]_TXCLK - MII Mode
            3. Table 5-27 Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode
            4. Table 5-28 Switching Characteristics for GMII[x]_TXD[3:0], and GMII[x]_TXEN - MII Mode
          4. 5.11.7.1.3 Ethernet MAC and Switch RMII Electrical Data and Timing
            1. Table 5-29 Timing Requirements for RMII[x]_REFCLK - RMII Mode
            2. Table 5-30 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
            3. Table 5-31 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
          5. 5.11.7.1.4 Ethernet MAC and Switch RGMII Electrical Data and Timing
            1. Table 5-32 Timing Requirements for RGMII[x]_RCLK - RGMII Mode
            2. Table 5-33 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
            3. Table 5-34 Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
            4. Table 5-35 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
      8. 5.11.8  External Memory Interfaces
        1. 5.11.8.1 General-Purpose Memory Controller (GPMC)
          1. 5.11.8.1.1 GPMC and NOR Flash—Synchronous Mode
            1. Table 5-36 GPMC and NOR Flash Timing Conditions—Synchronous Mode
            2. Table 5-37 GPMC and NOR Flash Timing Requirements—Synchronous Mode
            3. Table 5-38 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
          2. 5.11.8.1.2 GPMC and NOR Flash—Asynchronous Mode
            1. Table 5-39 GPMC and NOR Flash Timing Conditions—Asynchronous Mode
            2. Table 5-40 GPMC and NOR Flash Internal Timing Parameters—Asynchronous Mode
            3. Table 5-41 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
            4. Table 5-42 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
          3. 5.11.8.1.3 GPMC and NAND Flash—Asynchronous Mode
            1. Table 5-43 GPMC and NAND Flash Timing Conditions—Asynchronous Mode
            2. Table 5-44 GPMC and NAND Flash Internal Timing Parameters—Asynchronous Mode
            3. Table 5-45 GPMC and NAND Flash Timing Requirements—Asynchronous Mode
            4. Table 5-46 GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
        2. 5.11.8.2 Memory Interface
          1. 5.11.8.2.1 DDR3 and DDR3L Routing Guidelines
            1. 5.11.8.2.1.1 Board Designs
            2. 5.11.8.2.1.2 DDR3 Device Combinations
            3. 5.11.8.2.1.3 DDR3 Interface
              1. 5.11.8.2.1.3.1  DDR3 Interface Schematic
              2. 5.11.8.2.1.3.2  Compatible JEDEC DDR3 Devices
              3. 5.11.8.2.1.3.3  DDR3 PCB Stackup
              4. 5.11.8.2.1.3.4  DDR3 Placement
              5. 5.11.8.2.1.3.5  DDR3 Keepout Region
              6. 5.11.8.2.1.3.6  DDR3 Bulk Bypass Capacitors
              7. 5.11.8.2.1.3.7  DDR3 High-Speed Bypass Capacitors
                1. 5.11.8.2.1.3.7.1 Return Current Bypass Capacitors
              8. 5.11.8.2.1.3.8  DDR3 Net Classes
              9. 5.11.8.2.1.3.9  DDR3 Signal Termination
              10. 5.11.8.2.1.3.10 DDR3 DDR_VREF Routing
              11. 5.11.8.2.1.3.11 DDR3 VTT
            4. 5.11.8.2.1.4 DDR3 CK and ADDR_CTRL Topologies and Routing Definition
              1. 5.11.8.2.1.4.1 Using Two DDR3 Devices (x8 or x16)
                1. 5.11.8.2.1.4.1.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
                2. 5.11.8.2.1.4.1.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
              2. 5.11.8.2.1.4.2 Using Four 8-Bit DDR3 Devices
                1. 5.11.8.2.1.4.2.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
                2. 5.11.8.2.1.4.2.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
              3. 5.11.8.2.1.4.3 One 16-Bit DDR3 Device
                1. 5.11.8.2.1.4.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
                2. 5.11.8.2.1.4.3.2 CK and ADDR_CTRL Routing, One DDR3 Device
            5. 5.11.8.2.1.5 Data Topologies and Routing Definition
              1. 5.11.8.2.1.5.1 DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices
              2. 5.11.8.2.1.5.2 DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices
            6. 5.11.8.2.1.6 Routing Specification
              1. 5.11.8.2.1.6.1 CK and ADDR_CTRL Routing Specification
              2. 5.11.8.2.1.6.2 DQS[x] and DQ[x] Routing Specification
          2. 5.11.8.2.2 LPDDR2 Routing Guidelines
            1. 5.11.8.2.2.1 LPDDR2 Board Designs
            2. 5.11.8.2.2.2 LPDDR2 Device Configurations
            3. 5.11.8.2.2.3 LPDDR2 Interface
              1. 5.11.8.2.2.3.1 LPDDR2 Interface Schematic
              2. 5.11.8.2.2.3.2 Compatible JEDEC LPDDR2 Devices
              3. 5.11.8.2.2.3.3 LPDDR2 PCB Stackup
              4. 5.11.8.2.2.3.4 LPDDR2 Placement
              5. 5.11.8.2.2.3.5 LPDDR2 Keepout Region
              6. 5.11.8.2.2.3.6 LPDDR2 Net Classes
              7. 5.11.8.2.2.3.7 LPDDR2 Signal Termination
              8. 5.11.8.2.2.3.8 LPDDR2 DDR_VREF Routing
            4. 5.11.8.2.2.4 Routing Specification
              1. 5.11.8.2.2.4.1 DQS[x] and DQ[x] Routing Specification
              2. 5.11.8.2.2.4.2 CK and ADDR_CTRL Routing Specification
      9. 5.11.9  Display Subsystem (DSS)
      10. 5.11.10 Camera (VPFE)
      11. 5.11.11 Inter-Integrated Circuit (I2C)
        1. 5.11.11.1 I2C Electrical Data and Timing
          1. Table 5-69 I2C Timing Conditions - Slave Mode
          2. Table 5-70 Timing Requirements for I2C Input Timings
          3. Table 5-71 Switching Characteristics for I2C Output Timings
      12. 5.11.12 Multichannel Audio Serial Port (McASP)
        1. 5.11.12.1 McASP Device-Specific Information
        2. 5.11.12.2 McASP Electrical Data and Timing
          1. Table 5-72 McASP Timing Conditions
          2. Table 5-73 Timing Requirements for McASP
          3. Table 5-74 Switching Characteristics for McASP
      13. 5.11.13 Multichannel Serial Port Interface (McSPI)
        1. 5.11.13.1 McSPI Electrical Data and Timing
          1. 5.11.13.1.1 McSPI—Slave Mode
            1. Table 5-75 McSPI Timing Conditions—Slave Mode
            2. Table 5-76 Timing Requirements for McSPI Input Timings—Slave Mode
            3. Table 5-77 Switching Characteristics for McSPI Output Timings—Slave Mode
          2. 5.11.13.1.2 McSPI—Master Mode
            1. Table 5-78 McSPI Timing Conditions—Master Mode
            2. Table 5-79 Timing Requirements for McSPI Input Timings—Master Mode
            3. Table 5-80 Switching Characteristics for McSPI Output Timings—Master Mode
      14. 5.11.14 Quad Serial Port Interface (QSPI)
        1. Table 5-81 QSPI Switching Characteristics
      15. 5.11.15 HDQ/1-Wire Interface (HDQ/1-Wire)
        1. 5.11.15.1 HDQ Protocol
        2. 5.11.15.2 1-Wire Protocol
      16. 5.11.16 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
        1. 5.11.16.1 Programmable Real-Time Unit (PRU-ICSS PRU)
          1. Table 5-86  PRU-ICSS PRU Timing Conditions
          2. 5.11.16.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
            1. Table 5-87 PRU-ICSS PRU Timing Requirements - Direct Input Mode
            2. Table 5-88 PRU-ICSS PRU Switching Requirements - Direct Output Mode
          3. 5.11.16.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
            1. Table 5-89 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
          4. 5.11.16.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
            1. Table 5-90 PRU-ICSS PRU Timing Requirements - Shift In Mode
            2. Table 5-91 PRU-ICSS PRU Switching Requirements - Shift Out Mode
          5. 5.11.16.1.4 PRU-ICSS Sigma Delta Electrical Data and Timing
            1. Table 5-92 PRU-ICSS Timing Requirements - Sigma Delta Mode
          6. 5.11.16.1.5 PRU-ICSS ENDAT Electrical Data and Timing
            1. Table 5-93 PRU-ICSS Timing Requirements - ENDAT Mode
            2. Table 5-94 PRU-ICSS Switching Requirements - ENDAT Mode
        2. 5.11.16.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
          1. Table 5-95  PRU-ICSS ECAT Timing Conditions
          2. 5.11.16.2.1 PRU-ICSS ECAT Electrical Data and Timing
            1. Table 5-96  PRU-ICSS ECAT Timing Requirements - Input Validated With LATCH_IN
            2. Table 5-97  PRU-ICSS ECAT Timing Requirements - Input Validated With SYNCx
            3. Table 5-98  PRU-ICSS ECAT Timing Requirements - Input Validated With Start of Frame (SOF)
            4. Table 5-99  PRU-ICSS ECAT Timing Requirements - LATCHx_IN
            5. Table 5-100 PRU-ICSS ECAT Switching Requirements - Digital IOs
        3. 5.11.16.3 PRU-ICSS MII_RT and Switch
          1. Table 5-101 PRU-ICSS MII_RT Switch Timing Conditions
          2. 5.11.16.3.1 PRU-ICSS MDIO Electrical Data and Timing
            1. Table 5-102 PRU-ICSS MDIO Timing Requirements - MDIO_DATA
            2. Table 5-103 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
            3. Table 5-104 PRU-ICSS MDIO Switching Characteristics - MDIO_DATA
          3. 5.11.16.3.2 PRU-ICSS MII_RT Electrical Data and Timing
            1. Table 5-105 PRU-ICSS MII_RT Timing Requirements - MII_RXCLK
            2. Table 5-106 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
            3. Table 5-107 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
            4. Table 5-108 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
        4. 5.11.16.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
          1. Table 5-109 Timing Requirements for PRU-ICSS UART Receive
          2. Table 5-110 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
      17. 5.11.17 Multimedia Card (MMC) Interface
        1. 5.11.17.1 MMC Electrical Data and Timing
          1. Table 5-111 MMC Timing Conditions
          2. Table 5-112 Timing Requirements for MMC[0]_CMD and MMC[0]_DAT[7:0]
          3. Table 5-113 Timing Requirements for MMC[1/2]_CMD and MMC[1/2]_DAT[7:0]
          4. Table 5-114 Switching Characteristics for MMC[x]_CLK
          5. Table 5-115 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—HSPE=0
          6. Table 5-116 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—HSPE=1
      18. 5.11.18 Universal Asynchronous Receiver/Transmitter (UART)
        1. 5.11.18.1 UART Electrical Data and Timing
          1. Table 5-117 Timing Requirements for UARTx Receive
          2. Table 5-118 for UARTx Transmit
        2. 5.11.18.2 UART IrDA Interface
    12. 5.12 Emulation and Debug
      1. 5.12.1 IEEE 1149.1 JTAG
        1. 5.12.1.1 JTAG Electrical Data and Timing
          1. Table 5-121 Timing Requirements for JTAG
          2. Table 5-122 Switching Characteristics for JTAG
  6. 6Device and Documentation Support
    1. 6.1 Device Nomenclature
    2. 6.2 Tools and Software
    3. 6.3 Documentation Support
    4. 6.4 Community Resources
    5. 6.5 Trademarks
    6. 6.6 Electrostatic Discharge Caution
    7. 6.7 Glossary
  7. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 Via Channel
    2. 7.2 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZDN|491
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.2 Tools and Software

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.

Models

Design Kits and Evaluation Modules

    AMIC120 Industrial Development Kit (IDK)An application development platform for evaluating the industrial communication and control capabilities of the Sitara AM4379, AM4377, and AMIC120 processor for industrial applications.

TI Designs

    Sercos III Slave For AM437x Communication Development Platform Reference DesignCombines the AM437x Sitara processor family from Texas Instruments (TI) and the Sercos III media access control (MAC) layer into a single system-on-chip (SoC) solution. Targeted for Sercos III slave communications, the TIDEP0039 allows designers to implement the real-time Sercos III communication standard for a broad range of industrial automation equipment.
    EnDat 2.2 System Reference DesignImplements the EnDat 2.2 Master protocol stack and hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of the EnDat 2.2 Master protocol stack, half-duplex communications using RS485 transceivers and the line termination implemented on the Sitara AM437x Industrial Development Kit.
    Acontis EtherCAT Master Stack Reference DesignA highly portable software stack that can be used on various embedded platforms. The EC-Master supports the high performane TI Sitara MPUs, it provides a sophisticated EtherCAT Master solution which customers can use to implement EtherCAT communication interface boards, EtherCAT based PLC or motion control applications.
    Single Chip Drive for Industrial Communications and Motor ControlImplements a hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The platform also allows designers to implement real-time EtherCAT communications standards in a broad range of industrial automation equipment.
    AM437x Low Power Suspend Mode with LPDDR2Realizes processor power consumption less than 0.1 mW while keeping LPDDR2 memory in self refresh consuming ~ 1.6 mW. The system solution is comprised of AM437x Sitara processor, LPDDR2 memory and TPS65218 power management IC and optimized for new low power mode along with support for legacy low power modes.
    AM437x Discrete Power Reference DesignProvides flexibility to power designers. This reference design implementation is a BOM-optimized discrete power solution for the AMIC120 and AM437x processors with a minimal number of discrete ICs and basic feature set. T
    Embedded USB 2.0 Reference DesignThe USB 2.0 reference design guidelines are extremely important for designers considering USB2.0 electrical compliance testing. The guidelines are applicable to AM335x, AMIC120, and AM437x but also generic to other processors. The approach taken for these guidelines is highly practical, without complex formulas or theory.
    ARM MPU with Integrated HIPERFACE DSL Master Interface Reference DesignImplementation of HIPERFACE DSL Master protocol on Industrial Communication Sub-System (PRU-ICSS). The two wire interface allows for integration of position feedback wires into motor cable. Complete solution consists of AM437x PRU-ICSS firmware and TIDA-00177 transceiver reference design.

Software

    Processor SDK for AM437X Sitara Processors - Linux and TI-RTOS SupportA unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos. All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly reuse and migrate software across devices.
    TI Dual-Mode Bluetooth® StackComprised of Single-Mode and Dual-Mode offerings implementing the Bluetooth 4.0 specification. The Bluetooth stack is fully Bluetooth Special Interest Group (SIG) qualified, certified and royalty-free, provides simple command line sample applications to speed development, and upon request has MFI capability.

Development Tools

    Pin Mux ToolProvides a Graphical User Interface for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs. Results are output as C header/code files that can be imported into software development kits (SDK) or used to configure customer's custom software. Version 3 of the Pin Mux utility adds the capability of automatically selecting a mux configuration that satisfies the entered requirements.
    Power Estimation Tool (PET)Provides users the ability to gain insight in to the power consumption of select TI processors. The tool includes the ability for the user to choose multiple application scenarios and understand the power consumption as well as how advanced power saving techniques can be applied to further reduce overall power consumption.
    XDS200 USB Debug ProbeConnects to the target board via a TI 20-pin connector (with multiple adapters for TI 14-pin, ARM 10-pin and ARM 20-pin) and to the host PC via USB2.0 High Speed (480Mbps). It also requires a license of Code Composer Studio IDE running on the host PC.
    XDS560v2 System Trace USB and Ethernet Debug ProbeAdds system pin trace in its large external memory buffer. Available for selected TI devices, this external memory buffer captures device-level information that allows obtaining accurate bus performance activity and throughput, as well as power management of core and peripherals. Also, all XDS debug probes support Core and System Trace in all ARM and DSP processors that feature an Embedded Trace Buffer (ETB).
    XDS560v2 System Trace USB Debug ProbeAdds system pin trace in its large external memory buffer. Available for selected TI devices, this external memory buffer captures device-level information that allows obtaining accurate bus performance activity and throughput, as well as power management of core and peripherals. Also, all XDS debug probes support Core and System Trace in all ARM and DSP processors that feature an Embedded Trace Buffer (ETB).