SWRS188D May 2017 – December 2021 AWR1243
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VDDIN | 1.2 V digital power supply | 1.14 | 1.2 | 1.32 | V |
VIN_SRAM | 1.2 V power rail for internal SRAM | 1.14 | 1.2 | 1.32 | V |
VNWA | 1.2 V power rail for SRAM array back bias | 1.14 | 1.2 | 1.32 | V |
VIOIN | I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this supply. |
3.135 | 3.3 | 3.465 | V |
1.71 | 1.8 | 1.89 | |||
VIOIN_18 | 1.8 V supply for CMOS IO | 1.71 | 1.8 | 1.9 | V |
VIN_18CLK | 1.8 V supply for clock module | 1.71 | 1.8 | 1.9 | V |
VIOIN_18DIFF | 1.8 V supply for CSI2 port | 1.71 | 1.8 | 1.9 | V |
VIN_13RF1 | 1.3 V Analog and RF supply. VIN_13RF1 and VIN_13RF2 could be shorted on the board | 1.23 | 1.3 | 1.36 | V |
VIN_13RF2 | |||||
VIN_13RF1 (1-V Internal LDO bypass mode) |
0.95 | 1 | 1.05 | V | |
VIN_13RF2 (1-V Internal LDO bypass mode) |
|||||
VIN18BB | 1.8-V Analog baseband power supply | 1.71 | 1.8 | 1.9 | V |
VIN_18VCO | 1.8V RF VCO supply | 1.71 | 1.8 | 1.9 | V |
VIH | Voltage Input High (1.8 V mode) | 1.17 | V | ||
Voltage Input High (3.3 V mode) | 2.25 | ||||
VIL | Voltage Input Low (1.8 V mode) | 0.3*VIOIN | V | ||
Voltage Input Low (3.3 V mode) | 0.62 | ||||
VOH | High-level output threshold (IOH = 6 mA) | VIOIN – 450 | mV | ||
VOL | Low-level output threshold (IOL = 6 mA) | 450 | mV | ||
NRESET SOP[2:0] | VIL (1.8V Mode) | 0.2 | V | ||
VIH (1.8V Mode) | 0.96 | ||||
VIL (3.3V Mode) | 0.3 | ||||
VIH (3.3V Mode) | 1.57 |