SWRS188D May   2017  – December 2021 AWR1243

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Signal Descriptions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Power-On Hours (POH)
    4. 8.4 Recommended Operating Conditions
    5. 8.5 Power Supply Specifications
    6. 8.6 Power Consumption Summary
    7. 8.7 RF Specification
    8. 8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 8.9 Timing and Switching Characteristics
      1. 8.9.1 Power Supply Sequencing and Reset Timing
      2. 8.9.2 Synchronized Frame Triggering
      3. 8.9.3 Input Clocks and Oscillators
        1. 8.9.3.1 Clock Specifications
      4. 8.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.9.4.1 Peripheral Description
          1. 8.9.4.1.1 SPI Timing Conditions
          2. 8.9.4.1.2 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          3. 8.9.4.1.3 SPI Peripheral Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        2. 8.9.4.2 Typical Interface Protocol Diagram (Peripheral Mode)
      5. 8.9.5 LVDS Interface Configuration
        1. 8.9.5.1 LVDS Interface Timings
      6. 8.9.6 General-Purpose Input/Output
        1. 8.9.6.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 8.9.7 Camera Serial Interface (CSI)
        1. 8.9.7.1 CSI Switching Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Host Interface
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Data Format Over CSI2 Interface
  10. 10Monitoring and Diagnostics
    1. 10.1 Monitoring and Diagnostic Mechanisms
  11. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Short-, Medium-, and Long-Range Radar
    3. 11.3 Reference Schematic
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tray Information for

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABL|161
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.7 RF Specification

over recommended operating conditions and with run time calibrations enabled (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
Receiver Noise figure 76 to 77 GHz (VCO1) 14 dB
77 to 81 GHz (VCO2) 15
1-dB compression point (Out Of Band)(1) –8 dBm
Maximum gain 48 dB
Gain range 24 dB
Gain step size 2 dB
Image Rejection Ratio (IMRR) 30 dB
IF bandwidth(2) 15 MHz
ADC sampling rate (real/complex 2x) 37.5 Msps
ADC sampling rate (complex 1x) 18.75 Msps
ADC resolution 12 Bits
Return loss (S11) <–10 dB
Gain mismatch variation (over temperature) ±0.5 dB
Phase mismatch variation (over temperature) ±3 °
In-band IIP2 RX gain = 30dB
IF = 1.5, 2 MHz at
–12 dBFS		 16 dBm
Out-of-band IIP2 RX gain = 24dB
IF = 10 kHz at -10dBm,
1.9 MHz at -30 dBm		 24 dBm
Idle Channel Spurs –90 dBFS
Transmitter Output power 12 dBm
Amplitude noise –145 dBc/Hz
Clock subsystem Frequency range 76 81 GHz
Ramp rate 100 MHz/µs
Phase noise at 1-MHz offset 76 to 77 GHz (VCO1) –95 dBc/Hz
77 to 81 GHz (VCO2) –93
(1) 1-dB Compression Point (Out Of Band) is measured by feed a Continuous wave Tone (10 kHz) well below the lowest HPF cut-off frequency.
(2) The analog IF stages include high-pass filtering, with two independently configurable first-order high-pass corner frequencies. The set of available HPF corners is summarized as follows:
Available HPF Corner Frequencies (kHz)
HPF1 HPF2
175, 235, 350, 700 350, 700, 1400, 2800
The filtering performed by the digital baseband chain is targeted to provide:
  • Less than ±0.5 dB pass-band ripple/droop, and
  • Better than 60 dB anti-aliasing attenuation for any frequency that can alias back into the pass-band.

Figure 8-1 shows variations of noise figure and in-band P1dB parameters with respect to receiver gain programmed.

GUID-20210127-CA0I-13FG-JLLX-PFXSSG9TGFW9-low.gif Figure 8-1 Noise Figure, In-band P1dB vs Receiver Gain