SWRS222C december 2018 – january 2022 AWR1843
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
NO. | PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
1 | tc(SPC)S | Cycle time, SPICLK(4) | 25 | ns | ||
2(5) | tw(SPCH)S | Pulse duration, SPICLK high (clock polarity = 0) | 10 | ns | ||
tw(SPCL)S | Pulse duration, SPICLK low (clock polarity = 1) | 10 | ||||
3(5) | tw(SPCL)S | Pulse duration, SPICLK low (clock polarity = 0) | 10 | ns | ||
tw(SPCH)S | Pulse duration, SPICLK high (clock polarity = 1) | 10 | ||||
4(5) | td(SPCH-SOMI)S | Delay time, SPISOMI valid after SPICLK high (clock polarity = 0) | 10 | ns | ||
td(SPCL-SOMI)S | Delay time, SPISOMI valid after SPICLK low (clock polarity = 1) | 10 | ||||
5(5) | th(SPCH-SOMI)S | Hold time, SPISOMI data valid after SPICLK high (clock polarity = 0) | 2 | ns | ||
th(SPCL-SOMI)S | Hold time, SPISOMI data valid after SPICLK low (clock polarity = 1) | 2 | ||||
4(5) | td(SPCH-SOMI)S | Delay time, SPISOMI valid after SPICLK high (clock polarity = 0; clock phase = 0) OR (clock polarity = 1; clock phase = 1) | 10 | ns | ||
td(SPCL-SOMI)S | Delay time, SPISOMI valid after SPICLK low (clock polarity = 1; clock phase = 0) OR (clock polarity = 0; clock phase = 1) | 10 | ||||
5(5) | th(SPCH-SOMI)S | Hold time, SPISOMI data valid after SPICLK high (clock polarity = 0; clock phase = 0) OR (clock polarity = 1; clock phase = 1) | 2 | ns | ||
th(SPCL-SOMI)S | Hold time, SPISOMI data valid after SPICLK low (clock polarity = 1; clock phase = 0) OR (clock polarity = 0; clock phase = 1) | 2 | ||||
6(5) | tsu(SIMO-SPCL)S | Setup time, SPISIMO before SPICLK low (clock polarity = 0; clock phase = 0) OR (clock polarity = 1; clock phase = 1) | 3 | ns | ||
tsu(SIMO-SPCH)S | Setup time, SPISIMO before SPICLK high (clock polarity = 1; clock phase = 0) OR (clock polarity = 0; clock phase = 1) | 3 | ||||
7(5) | th(SPCL-SIMO)S | Hold time, SPISIMO data valid after SPICLK low (clock polarity = 0; clock phase = 0) OR (clock polarity = 1; clock phase = 1) | 1 | ns | ||
th(SPCL-SIMO)S | Hold time, SPISIMO data valid after SPICLK high (clock polarity = 1; clock phase = 0) OR (clock polarity = 0; clock phase = 1) | 1 |