SWRS223D February   2020  – February 2024 AWR2243

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Power-On Hours (POH)
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Power Supply Specifications
    6. 7.6 Power Consumption Summary
    7. 7.7 RF Specification
    8. 7.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 7.9 Timing and Switching Characteristics
      1. 7.9.1 Power Supply Sequencing and Reset Timing
      2. 7.9.2 Synchronized Frame Triggering
      3. 7.9.3 Input Clocks and Oscillators
        1. 7.9.3.1 Clock Specifications
      4. 7.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.9.4.1 Peripheral Description
          1. 7.9.4.1.1 SPI Timing Conditions
          2. 7.9.4.1.2 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          3. 7.9.4.1.3 SPI Peripheral Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        2. 7.9.4.2 Typical Interface Protocol Diagram (Peripheral Mode)
      5. 7.9.5 Inter-Integrated Circuit Interface (I2C)
        1. 7.9.5.1 I2C Timing Requirements
      6. 7.9.6 LVDS Interface Configuration
        1. 7.9.6.1 LVDS Interface Timings
      7. 7.9.7 General-Purpose Input/Output
        1. 7.9.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      8. 7.9.8 Camera Serial Interface (CSI)
        1. 7.9.8.1 CSI Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
      2. 8.3.2 Host Interface
    4. 8.4 Other Subsystems
      1. 8.4.1 ADC Data Format Over CSI2 Interface
      2. 8.4.2 ADC Channels (Service) for User Application
        1. 8.4.2.1 GPADC Parameters
  10. 9 Monitoring and Diagnostic Mechanisms
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Short-, Medium-, and Long-Range Radar
    3. 10.3 Imaging Radar using Cascade Configuration
    4. 10.4 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Export Control Notice
    8. 11.8 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABL|161
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Power Supply Specifications

Table 7-1 describes the four rails from an external power supply block of the AWR2243 device.

Table 7-1 Power Supply Rails Characteristics
SUPPLYDEVICE BLOCKS POWERED FROM THE SUPPLYRELEVANT IOS IN THE DEVICE
1.8 VSynthesizer and APLL VCOs, crystal oscillator, IF Amplifier stages, ADC, CSI2Input: VIN_18VCO, VIN18CLK, VIN_18BB, VIOIN_18DIFF, VIOIN_18IO
LDO Output: VOUT_14SYNTH, VOUT_14APLL
1.3 V (or 1 V in internal LDO bypass mode)(1)Power Amplifier, Low Noise Amplifier, Mixers and LO DistributionInput: VIN_13RF2, VIN_13RF1
LDO Output: VOUT_PA
3.3 V (or 1.8 V for 1.8 V I/O mode)Digital I/OsInput VIOIN
1.2 VCore Digital and SRAMsInput: VDDIN, VIN_SRAM
(1) Three simultaneous transmitter operation is supported only in 1-V LDO bypass and PA LDO disable mode. In this mode 1V supply needs to be fed on the VOUT PA pin.

The 1.3V (1.0V) and 1.8V power supply ripple specifications mentioned in Table 7-2 are defined to meet a target spur level of –105dBc (RF Pin = –15dBm) at the RX. The spur and ripple levels have a dB to dB relationship, for example, a 1dB increase in supply ripple leads to a ~1dB increase in spur level. Values quoted are rms levels for a sinusoidal input applied at the specified frequency.

Table 7-2 Ripple Specifications
FREQUENCY (kHz)RF RAILVCO/IF RAIL
1.0 V (INTERNAL LDO BYPASS) (µVRMS)1.3 V (µVRMS)1.8 V (µVRMS)
137.5764883
27557621
55032211
1100246
2200118213
4400139319
66002211729