SWRS314A January   2024  – November 2024 AWR2544

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
  6. 5 Related Products
  7. 6 Pin Configurations and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions - Digital
    4. 6.4 Signal Descriptions - Analog
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.5.2 Hardware Requirements
      3. 7.5.3 Impact to Your Hardware Warranty
    6. 7.6  Power Supply Specifications
    7. 7.7  Power Consumption Summary
    8. 7.8  RF Specifications
    9. 7.9  Thermal Resistance Characteristics
    10. 7.10 Power Supply Sequencing and Reset Timing
    11. 7.11 Input Clocks and Oscillators
      1. 7.11.1 Clock Specifications
    12. 7.12 Peripheral Information
      1. 7.12.1 QSPI Flash Memory Peripheral
        1. 7.12.1.1 QSPI Timing Conditions
        2. 7.12.1.2 QSPI Timing Requirements #GUID-C38B9713-DC57-4B3B-8AFF-A79AF70E5A5A/GUID-97D19708-D87E-443B-9ADF-1760CFEF6F4C #GUID-C38B9713-DC57-4B3B-8AFF-A79AF70E5A5A/GUID-0A61EEC9-2B95-4C27-B219-18D27C8F9430
        3. 7.12.1.3 QSPI Switching Characteristics #GUID-D1480E86-4079-4A44-A68A-26C2D9F4506B/T4362547-64 #GUID-D1480E86-4079-4A44-A68A-26C2D9F4506B/T4362547-65
      2. 7.12.2 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.12.2.1 MibSPI Peripheral Description
        2. 7.12.2.2 MibSPI Transmit and Receive RAM Organization
          1. 7.12.2.2.1 SPI Timing Conditions
          2. 7.12.2.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-3DD8619F-41DB-47CF-9AF7-5916CFF97E61/T4362547-236 #GUID-3DD8619F-41DB-47CF-9AF7-5916CFF97E61/T4362547-237 #GUID-3DD8619F-41DB-47CF-9AF7-5916CFF97E61/T4362547-238
          3. 7.12.2.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-220CE6B8-D17E-48AF-BF69-AAEC97D55C95/T4362547-244 #GUID-220CE6B8-D17E-48AF-BF69-AAEC97D55C95/T4362547-245 #GUID-220CE6B8-D17E-48AF-BF69-AAEC97D55C95/T4362547-246
        3. 7.12.2.3 SPI Peripheral Mode I/O Timings
          1. 7.12.2.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-BF2B230C-8F03-4C6A-A240-6DFD0CEC87C8/T4362547-70 #GUID-BF2B230C-8F03-4C6A-A240-6DFD0CEC87C8/T4362547-71 #GUID-BF2B230C-8F03-4C6A-A240-6DFD0CEC87C8/T4362547-73
      3. 7.12.3 Ethernet Switch (RGMII/RMII/MII) Peripheral
        1. 7.12.3.1  RGMII/RMII/MII Timing Conditions
        2. 7.12.3.2  RGMII Transmit Clock Switching Characteristics
        3. 7.12.3.3  RGMII Transmit Data and Control Switching Characteristics
        4. 7.12.3.4  RGMII Receive Clock Timing Requirements
        5. 7.12.3.5  RGMII Receive Data and Control Timing Requirements
        6. 7.12.3.6  RMII Transmit Clock Switching Characteristics
        7. 7.12.3.7  RMII Transmit Data and Control Switching Characteristics
        8. 7.12.3.8  RMII Receive Clock Timing Requirements
        9. 7.12.3.9  RMII Receive Data and Control Timing Requirements
        10. 7.12.3.10 MII Transmit Switching Characteristics
        11. 7.12.3.11 MII Receive Clock Timing Requirements
        12. 7.12.3.12 MII Receive Timing Requirements
        13. 7.12.3.13 MII Transmit Clock Timing Requirements
        14. 7.12.3.14 MDIO Interface Timings
      4. 7.12.4 LVDS Instrumentation and Measurement Peripheral
        1. 7.12.4.1 LVDS Interface Configuration
        2. 7.12.4.2 LVDS Interface Timings
      5. 7.12.5 UART Peripheral
        1. 7.12.5.1 SCI Timing Requirements
      6. 7.12.6 Inter-Integrated Circuit Interface (I2C)
        1. 7.12.6.1 I2C Timing Requirements #GUID-5F6D5D17-1161-44B3-ABD1-283215937B93/T4362547-185
      7. 7.12.7 Enhanced Pulse-Width Modulator (ePWM)
      8. 7.12.8 General-Purpose Input/Output
        1. 7.12.8.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) #GUID-918A19D2-41ED-481C-96AE-E1C69B8B3446/T4362547-45 #GUID-918A19D2-41ED-481C-96AE-E1C69B8B3446/T4362547-50
    13. 7.13 Emulation and Debug
      1. 7.13.1 Emulation and Debug Description
      2. 7.13.2 JTAG Interface
        1. 7.13.2.1 Timing Requirements for IEEE 1149.1 JTAG
        2. 7.13.2.2 Switching Characteristics for IEEE 1149.1 JTAG
      3. 7.13.3 ETM Trace Interface
        1. 7.13.3.1 ETM TRACE Timing Requirements
        2. 7.13.3.2 ETM TRACE Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 RF Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
      2. 8.3.2 Processor Subsystem
      3. 8.3.3 Automotive Interfaces
    4. 8.4 Other Subsystems
      1. 8.4.1 Hardware Accelerator Subsystem
      2. 8.4.2 Security – Hardware Security Module
      3. 8.4.3 ADC Channels (Service) for User Application
  10. 9 Monitoring and Diagnostics
    1. 9.1 Monitoring and Diagnostic Mechanisms
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Short and Medium Range Radar
    3. 10.3 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation support
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • AMQ|248
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3 Signal Descriptions - Digital

Note: All digital IO pins of the device (except NERROR_OUT and WARM_RESET) are non-failsafe; hence, care needs to be taken that they are not driven externally without the VIO supply being present to the device.
Note: The GPIO state during the power supply ramp is not ensured. In case the GPIO is used in the application where the state of the GPIO is critical, even when NRESET is low , a tri-state buffer should be used to isolate the GPIO output from the radar device and a pull resister used to define the required state in the application. The NRESET signal to the radar device could be used to control the output enable (OE) of the tri-state buffer.
FUNCTIONSIGNAL NAMEPIN TYPEDESCRIPTIONBALL NUMBER
SPI InterfaceMSS_MIBSPIB_CLKOSPI Channel B - Clock

R1, T7

MSS_MIBSPIB_SDOOSPI Channel B - Serial Data Out

T3

MSS_MIBSPIB_SDIISPI Channel B - Serial Data In

U2

MSS_MIBSPIB_CS0OSPI Channel B - Chip Select 0

T1, T6

MSS_MIBSPIB_CS1OSPI Channel B - Chip Select 1

U3, U4, T2

MSS_MIBSPIB_CS2OPI Channel B - Chip Select 2

T2, U7

UART (MSS)MSS_UARTA_RXIMain Subsystem - UART A Receive (For Flash programming)

P1, A10, A11, B8, R1

MSS_UARTA_TXIOMain Subsystem - UART A Transmit (For Flash programming)

R2, A6, A16, B7, P2, T1

MSS_UARTB_TXIOMain Subsystem - UART B Transmit

P2, A8, A16, B4, B6, N17, R1, R2, T1, T4

MSS_UARTB_RXIMain Subsystem - UART B Receive

A11, C17, P1, U16

QSPI for Serial FlashMSS_QSPI_0IOQSPI Data Line #0 (Used with Serial Data Flash)

U8

MSS_QSPI_1IQSPI Data Line #1 (Used with Serial Data Flash)

U7

MSS_QSPI_2IQSPI Data Line #2 (Used with Serial Data Flash)

U6

MSS_QSPI_3IQSPI Data Line #3 (Used with Serial Data Flash)

T5

MSS_QSPI_CLKIOQSPI clock (Used with Serial Data Flash)

T7

MSS_QSPI_CSOQSPI chip select (Used with Serial Data Flash)

T6

I2C interfaceMSS_I2C_SCLIOI2C Clock

R12, A10, A11, U2

MSS_I2C_SDAIOI2C Data

T12, A6, A16, T3

RS232 UARTMSS_RS232_RXIODebug UART (Operates as Bus Master) - Receive Signal

A11

MSS_RS232_TXIODebug UART (Operates as Bus Master) - Transmit Signal

A16

PWM ModuleMSS_EPWMA0OPWM Module 1 - Output A0

A9, A16, B9, M17, T3

MSS_EPWMA1OPWM Module 1 - Output A1

A16, B10, B11, U5, T13

MSS_EPWMA_SYNCIIPWM Module 1 - Sync Input

U4

MSS_EPWMA_SYNCOOPWM Module 1 - Sync Output
MSS_EPWMB0OPWM Module 2 - Output B0

A7, A11, A16, B10, T2, U2, U5, U16

MSS_EPWMB1OPWM Module 2 - Output B1

A8, A11, T2, T12

MSS_EPWMB_SYNCIIPWM Module 2 - Sync Input

B9, P2

MSS_EPWMB_SYNCOOPWM Module 2 - Sync Output

A7

MSS_EPWMC0OPWM Module 3 - Output C0

A11, B18, N17, R1

MSS_EPWMC1OPWM Module 3 - Output C1

A17, R12

MSS_EPWMC_SYNCIIPWM Module 3 - Sync Input

A10

MSS_EPWMC_SYNCOOPWM Module 3 - Sync Output

B11

MSS_EPWM_TZ0IPWM module Trip Signal 0

A17, T4

MSS_EPWM_TZ1IPWM module Trip Signal 1

B18, U4

MSS_EPWM_TZ2IPWM module Trip Signal 2

A8, U5

RGMII/RMII/MII EthernetMSS_MII_COLI

MSS Ethernet MII Collision Detect

T13

MSS_MII_CRSI

MSS Ethernet MII Carrier Sense

T12

MSS_MII_RXERIMSS Ethernet MII Receive Error

R12

MSS_MII_TXENOMSS Ethernet MII Transmit Enable

M17

MSS_MII_RXDVI

MSS Ethernet MII Receive Data Valid

U16

MSS_MII_TXD3OMSS Ethernet MII Transmit Data 3

N17

MSS_MII_TXD2OMSS Ethernet MII Transmit Data 2

T18

MSS_MII_TXD1

O

MSS Ethernet MII Transmit Data 1

P17

MSS_MII_TXD0OMSS Ethernet MII Transmit Data 0

R17

MSS_MII_TXCLKIMSS Ethernet MII Transmit Clock

T17

MSS_MII_RXCLKIMSS Ethernet MII Receive Clock

U15

MSS_MII_RXD3IMSS Ethernet MII Receive Data 3

U17

MSS_MII_RXD2IMSS Ethernet MII Receive Data 2

R16

MSS_MII_RXD1IMSS Ethernet MII Receive Data 1

T16

MSS_MII_RXD0IMSS Ethernet MII Receive Data 0

T15

MSS_RMII_REFCLKIOMSS Ethernet RMII Clock Input

T13

MSS_RMII_CRS_DVI

MSS Ethernet RMII Carrier Sense/Receive Data Valid

T12

MSS_RMII_RXERIMSS Ethernet RMII Receive Error

R12

MSS_RMII_TXENOMSS Ethernet RMII Transmit Enable

M17

MSS_RMII_TXD1OMSS Ethernet RMII Transmit Data 1

P17

MSS_RMII_TXD0OMSS Ethernet RMII Transmit Data 0

R17

MSS_RMII_RXD1IMSS Ethernet MII Receive Data 1

T16

MSS_RMII_RXD0IMSS Ethernet MII Receive Data 0

T15

MSS_RGMII_TCTLOMSS Ethernet RGMII Transmit Control

M17

MSS_RGMII_RCTLIMSS Ethernet RGMII Receive Control

U16

MSS_RGMII_TD3OMSS Ethernet RGMII Transmit Data 3

N17

MSS_RGMII_TD2OMSS Ethernet RGMII Transmit Data 2

T18

MSS_RGMII_TD1OMSS Ethernet RGMII Transmit Data 1

P17

MSS_RGMII_TD0OMSS Ethernet RGMII Transmit Data 0

R17

MSS_RGMII_TCLKOMSS Ethernet RGMII Transmit Clock

T17

MSS_RGMII_RCLKIMSS Ethernet RGMII Receive Clock

U15

MSS_RGMII_RD3IMSS Ethernet RGMII Receive Data 3

U17

MSS_RGMII_RD2IMSS Ethernet RGMII Receive Data 2

R16

MSS_RGMII_RD1IMSS Ethernet RGMII Receive Data 1

T16

MSS_RGMII_RD0IMSS Ethernet RGMII Receive Data 0

T15

MSS_MDIO_DATAIOMSS Ethernet Manage Data Input/Output data

T14

MSS_MDIO_CLKOMSS Ethernet Manage Data Input/Output Clock

U14

MSS_CPTS0_TS_SYNCOEthernet Timestamp SYNC output

P1

MSS_CPTS0_HW2TSPUSHIEthernet Hardware Timestamp Input Pin

A8, A17, R2

MSS_CPTS0_HW1TSPUSHIEthernet Hardware Timestamp Input Pin

A7, B18

Trace SignalTRACE_DATA_0ODebug Trace Output - Data Line

A6

TRACE_DATA_1ODebug Trace Output - Data Line

A10

TRACE_DATA_2ODebug Trace Output - Data Line

B9

TRACE_DATA_3ODebug Trace Output - Data Line

B11

TRACE_DATA_4ODebug Trace Output - Data Line

A7

TRACE_DATA_5ODebug Trace Output - Data Line

A8

TRACE_DATA_6ODebug Trace Output - Data Line

B18

TRACE_DATA_7ODebug Trace Output - Data Line

A17

TRACE_CLKODebug Trace Output - Clock

A9

TRACE_CTLODebug Trace Output - Control

B10

General-purpose I/OsMSS_GPIO_0IOGeneral-purpose I/O

U5, A10, P2

MSS_GPIO_1IOGeneral-purpose I/O

U4, B9

MSS_GPIO_2IOGeneral-purpose I/O

T4, B11

MSS_GPIO_3IOGeneral-purpose I/O

A7

MSS_GPIO_4IOGeneral-purpose I/O

A8, T1

MSS_GPIO_5IOGeneral-purpose I/O

B18, R1

MSS_GPIO_6IOGeneral-purpose I/O

A17, T6

MSS_GPIO_7IOGeneral-purpose I/O

T7

MSS_GPIO_8IOGeneral-purpose I/O

B9, P1, U8

MSS_GPIO_9IOGeneral-purpose I/O

B11, R2, U7

MSS_GPIO_10IOGeneral-purpose I/O

B18, U6

MSS_GPIO_11IOGeneral-purpose I/O

A17, T5

MSS_GPIO_12IOGeneral-purpose I/O

P1, U2

MSS_GPIO_13IOGeneral-purpose I/O

R2, U5

MSS_GPIO_14IOGeneral-purpose I/O

A16

MSS_GPIO_15IOGeneral-purpose I/O

A11

MSS_GPIO_16IOGeneral-purpose I/O

U4

MSS_GPIO_17IOGeneral-purpose I/O

T13, B6

MSS_GPIO_18IOGeneral-purpose I/O

B5, T12

MSS_GPIO_19IOGeneral-purpose I/O

R12

MSS_GPIO_20IOGeneral-purpose I/O

M17

MSS_GPIO_21IOGeneral-purpose I/O

U16, T3

MSS_GPIO_22IOGeneral-purpose I/O

N17, U2

MSS_GPIO_23IOGeneral-purpose I/O

B8, T18

MSS_GPIO_24IOGeneral-purpose I/O

A17, B7, P17

MSS_GPIO_25IOGeneral-purpose I/O

A9, B18, R17

MSS_GPIO_26IOGeneral-purpose I/O

A8, T4, T17

MSS_GPIO_27IOGeneral-purpose I/O

A7, B10, U15

MSS_GPIO_28IOGeneral-purpose I/O

B11, C17, U17

MSS_GPIO_29IOGeneral-purpose I/O

B9, R16, T2

MSS_GPIO_30IOGeneral-purpose I/O

A10, T14, T16

MSS_GPIO_31IOGeneral-purpose I/O

A6, P2, T15, U14

Chirp/Frame signalsADC_VALIDOWhen high, indicating valid ADC samples

A7, B9, B11, C17, T5, U3, U6

CHIRP_STARTOPulse signal indicating the start of each chirp

B9, B10, B11, B18, T4

CHIRP_ENDOPulse signal indicating the end of each chirp

A17, B9, B10, B11, T4

FRAME_STARTOPulse signal indicating the start of each frame

A9, B9, B10, B11, T4

LVDS_VALIDLVDS_VALIDOWhen high, indicating valid LVDS data

A9, A16, B10, P2, T2, T4, U4

External clock outMCU_CLKOUTOProgrammable clock given out to external MCU or the processor

A9

PMIC_CLKOUTOOutput Clock from the device for PMIC

B10, T4, U5

System SynchronizationHW_SYNCINILow frequency Synchronization signal input

C17

SYNC_OUTOLow Frequency Synchronization Signal output

C17, T2, T4, U4

Clock OutputOBS_CLKOUTODebug Clock Output

A9, B10

RCOSC_CLKODebug Clock Output

T2

Reference ClockXREF_CLK0IExternal reference input clock 0

A8

XREF_CLK1IExternal reference input clock 1

A7

JTAGTCKIJTAG Test Clock

B6

TMSIOJTAG Test Mode Signal

B5

TDIIJTAG Test Data Input

B8

TDOOJTAG Test Data Output

B7

UART (BSS)BSS_UARTA_TXODebug UART Transmit [Radar Block]

B18, A16, A11, B5, B7, R1, T1, U4

BSS_UARTA_RXIDebug UART Receive [Radar Block]

A9, B6

ResetWARM_RESETIOOpen drain fail safe warm reset signal. Can be driven from PMIC for diagnostic or can be used as status signal that the device is going through reset.

B17

SafetyNERROR_OUTOOpen drain fail safe output signal. Connected to PMIC/Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset.

D17

Sense On powerSOP[0]IThe SOP pins are driven externally (weak drive) and the mmWave device senses the state of these pins during bootup to decide the bootup mode. After boot the same pins have other functionality.
  • [SOP2 SOP1 SOP0] = [0 0 1] -> Functional QSPI load mode
  • [SOP2 SOP1 SOP0] = [1 0 1] -> UART load mode
  • [SOP2 SOP1 SOP0] = [0 1 1] -> debug and development mode
  • [SOP2 SOP1 SOP0] = [1 1 0] -> JTAG load mode for customer key provisioning
The following configurations of SOP pins help decide the reference crystal frequency
  • [SOP4 SOP3] = [0 0] -> 40 MHz
  • [SOP4 SOP3] = [1 1] -> 50 MHz

B7

SOP[1]I

T2

SOP[2]I

B10

SOP[3]I

P2

SOP[4]I

R2

CSI2 / LVDSCSI2_TXM0 / LVDS_TXM0OCSI2 / LVDS Transmitter, Differential Data Output, Lane 0

K17

CSI2_TXP0 / LVDS_TXP0

O

K18

CSI2_TXM4 / LVDS_CLKM

OCSI2 / LVDS Differential Clock

L17

CSI2_TXP4 / LVDS_CLKPO

L18

CSI2_CLKM / CSI2_TXM2 / LVDS_FRCLKMOCSI2 / LVDS Differential Frame Clock

F17

CSI2_CLKP / CSI2_TXP2 / LVDS_FRCLKMPO

F18

CSI2_TXM1 / LVDS_TXM1

O

CSI2 / LVDS Transmitter, Differential Data Output, Lane 1

J17

CSI2_TXP1 / LVDS_TXP1

O

J18

CSI2_TXM3

0

CSI2 Transmitter - Differential Data Output

G17

CSI2_TXP3

0

CSI2 Transmitter - Differential Data Output

G18