SWRS314 January   2024 AWR2544

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
  6. 5 Related Products
  7. 6 Pin Configurations and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions - Digital
    4. 6.4 Signal Descriptions - Analog
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.5.2 Hardware Requirements
      3. 7.5.3 Impact to Your Hardware Warranty
    6. 7.6  Power Supply Specifications
    7. 7.7  Power Consumption Summary
    8. 7.8  RF Specifications
    9. 7.9  Thermal Resistance Characteristics
    10. 7.10 Power Supply Sequencing and Reset Timing
    11. 7.11 Input Clocks and Oscillators
      1. 7.11.1 Clock Specifications
    12. 7.12 Peripheral Information
      1. 7.12.1 QSPI Flash Memory Peripheral
        1. 7.12.1.1 QSPI Timing Conditions
        2. 7.12.1.2 QSPI Timing Requirements #GUID-C38B9713-DC57-4B3B-8AFF-A79AF70E5A5A/GUID-97D19708-D87E-443B-9ADF-1760CFEF6F4C #GUID-C38B9713-DC57-4B3B-8AFF-A79AF70E5A5A/GUID-0A61EEC9-2B95-4C27-B219-18D27C8F9430
        3. 7.12.1.3 QSPI Switching Characteristics #GUID-D1480E86-4079-4A44-A68A-26C2D9F4506B/T4362547-64 #GUID-D1480E86-4079-4A44-A68A-26C2D9F4506B/T4362547-65
      2. 7.12.2 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.12.2.1 MibSPI Peripheral Description
        2. 7.12.2.2 MibSPI Transmit and Receive RAM Organization
          1. 7.12.2.2.1 SPI Timing Conditions
          2. 7.12.2.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-3DD8619F-41DB-47CF-9AF7-5916CFF97E61/T4362547-236 #GUID-3DD8619F-41DB-47CF-9AF7-5916CFF97E61/T4362547-237 #GUID-3DD8619F-41DB-47CF-9AF7-5916CFF97E61/T4362547-238
          3. 7.12.2.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-220CE6B8-D17E-48AF-BF69-AAEC97D55C95/T4362547-244 #GUID-220CE6B8-D17E-48AF-BF69-AAEC97D55C95/T4362547-245 #GUID-220CE6B8-D17E-48AF-BF69-AAEC97D55C95/T4362547-246
        3. 7.12.2.3 SPI Peripheral Mode I/O Timings
          1. 7.12.2.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-BF2B230C-8F03-4C6A-A240-6DFD0CEC87C8/T4362547-70 #GUID-BF2B230C-8F03-4C6A-A240-6DFD0CEC87C8/T4362547-71 #GUID-BF2B230C-8F03-4C6A-A240-6DFD0CEC87C8/T4362547-73
      3. 7.12.3 Ethernet Switch (RGMII/RMII/MII) Peripheral
        1. 7.12.3.1  RGMII/RMII/MII Timing Conditions
        2. 7.12.3.2  RGMII Transmit Clock Switching Characteristics
        3. 7.12.3.3  RGMII Transmit Data and Control Switching Characteristics
        4. 7.12.3.4  RGMII Receive Clock Timing Requirements
        5. 7.12.3.5  RGMII Receive Data and Control Timing Requirements
        6. 7.12.3.6  RMII Transmit Clock Switching Characteristics
        7. 7.12.3.7  RMII Transmit Data and Control Switching Characteristics
        8. 7.12.3.8  RMII Receive Clock Timing Requirements
        9. 7.12.3.9  RMII Receive Data and Control Timing Requirements
        10. 7.12.3.10 MII Transmit Switching Characteristics
        11. 7.12.3.11 MII Receive Clock Timing Requirements
        12. 7.12.3.12 MII Receive Timing Requirements
        13. 7.12.3.13 MII Transmit Clock Timing Requirements
        14. 7.12.3.14 MDIO Interface Timings
      4. 7.12.4 LVDS Instrumentation and Measurement Peripheral
        1. 7.12.4.1 LVDS Interface Configuration
        2. 7.12.4.2 LVDS Interface Timings
      5. 7.12.5 UART Peripheral
        1. 7.12.5.1 SCI Timing Requirements
      6. 7.12.6 Inter-Integrated Circuit Interface (I2C)
        1. 7.12.6.1 I2C Timing Requirements #GUID-5F6D5D17-1161-44B3-ABD1-283215937B93/T4362547-185
      7. 7.12.7 Enhanced Pulse-Width Modulator (ePWM)
      8. 7.12.8 General-Purpose Input/Output
        1. 7.12.8.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) #GUID-918A19D2-41ED-481C-96AE-E1C69B8B3446/T4362547-45 #GUID-918A19D2-41ED-481C-96AE-E1C69B8B3446/T4362547-50
    13. 7.13 Emulation and Debug
      1. 7.13.1 Emulation and Debug Description
      2. 7.13.2 JTAG Interface
        1. 7.13.2.1 Timing Requirements for IEEE 1149.1 JTAG
        2. 7.13.2.2 Switching Characteristics for IEEE 1149.1 JTAG
      3. 7.13.3 ETM Trace Interface
        1. 7.13.3.1 ETM TRACE Timing Requirements
        2. 7.13.3.2 ETM TRACE Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 RF Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
      2. 8.3.2 Processor Subsystem
      3. 8.3.3 Automotive Interfaces
    4. 8.4 Other Subsystems
      1. 8.4.1 Hardware Accelerator Subsystem
      2. 8.4.2 Security – Hardware Security Module
      3. 8.4.3 ADC Channels (Service) for User Application
  10. 9 Monitoring and Diagnostics
    1. 9.1 Monitoring and Diagnostic Mechanisms
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Short and Medium Range Radar
    3. 10.3 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Support
  13. 12Device Nomenclature
    1. 12.1 Tools and Software
    2. 12.2 Documentation support
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • AMQ|248
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Signal Descriptions - Analog

INTERFACESIGNAL NAMEPIN TYPEDESCRIPTIONBALL

NUMBER

Waveguide LaunchesTransmitterOWaveguide Launch for TX outputs
ReceiverIWaveguide Launch for RX inputs
ResetNRESETIPower on reset for chip. Active low. The NRESET needs to be pulled low for a minimum of 20 μsec to ensure proper device reset.

E17

Reference OscillatorCLKPIIn XTAL mode: Input for the reference crystal
In External clock mode: Single ended input reference clock port

F2

CLKMIIn XTAL mode: Feedback drive for the reference crystal
In External clock mode: Connect this port to ground

E1

Reference Clock for Ethernet

OSC_CLK_OUT_ETH

O

Can be used to replace 25MHz crystal used with Ethernet PHY IC (OSC_CLK_OUT_25 on EVM)

C1

Reference clockOSC_CLKOUTOReference clock output from clocking subsystem after cleanup PLL

(OSC_CLKTOP on EVM)

C2

Bandgap voltageVBGAPODevice's Band Gap Reference Output

K1

Power supplyVDDPower1.2V digital power supply

A15,D18,M14,M15,M16, N13,N15,P13,P15,R14,U9

VDD_SRAMPower1.2V power rail for internal SRAM

U13

VNWAPower1.2V power rail for SRAM array back bias

C18

VIOINPowerI/O Supply (3.3V or 1.8V): All CMOS I/Os would operate on this supply

A12, N18, U12

VIOIN_18Power1.8V supply for CMOS IO

A13, R18, U10

VDDA_18CLKPower1.8V supply for clock module

A2

VDDA_18PMPower1.8V supply for PM module

K2

VIOIN_18CSIPower1.8V supply for CSI port

H18

VPPPowerVoltage supply for fuse chain

M18

Power supplyVDDA_10RF1Power1V Analog and RF supply,VDDA_10RF1 and VDDA_10RF2 could be shorted on the board

M1

VDDA_10RF2Power1V Analog and RF supply

A3,A4

VDDA_18BBPower1.8V Analog base band power supply

N1

VDDA_18VCOPower1.8V RF VCO supply

J2

VSS(2)GroundDigital ground

A14,A18,E18,H12,H17,J12,L14,L16,M12,P12,P18,U1, U11,U18

VSSA(3)GroundAnalog ground

A1,A5,B1,B2,B3,B4,B12, B13,B14,B15,B16,C3,C4,C5,C6,C7,C8,C9,C10,C11,C12, C16,D1,D2,D3,D7,D8,D11, D12,D16,E2,E3,E7,E8,E11, E12,E13,E14,E15,E16,F1, F3,F4,F5,F6,F7,F8,F11,F12,F13,F14,F15,F16,G1,G2,G3,G4,G5,G6,G8,G9,G10,G11, G12,G13,G16,H3,H6,H7,H8,H9,H10,H11,H13,H16,J1, J3,J6,J7,J11,J13,J16,K3,K6, K7,K11,K13,K14,K15,K16, L3,L4,L5,L6,L7,L8,L9,L10, L11,M3,M4,M5,M6,M7, M8,M9,M10,M11,N3,N7, N8,N11,P3,P7,P8,P11,R3, R4,R5,R6,R7,R8,R11, T8,T9,T10,T11

Internal LDO output/inputsVOUT_14APLLOInternal LDO output

H2

VOUT_14SYNTHOInternal LDO output

H1

General purpose ADC inputs for external voltage monitoring(1)ADC1IADC Channel 1

L2

ADC2IADC Channel 2

L1

ADC5I

ADC Channel 5

N2

ADC6I

ADC Channel 6

M2

(1) For details, see Section 8.4.3
(2) Corner BGAs are VSS and redundant, meaning if they fail, the device will still function.
(3) The VSSA BGAs around the launches are not redundant and are required for functionality.