SWRS246C November   2020  – July 2022 AWR6843AOP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Pin Functions - Digital and Analog [ALP Package]
    3. 7.3 Pin Attributes
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Power Supply Specifications
    6. 8.6  Power Consumption Summary
    7. 8.7  RF Specification
    8. 8.8  CPU Specifications
    9. 8.9  Thermal Resistance Characteristics for FCBGA Package [ALP0180A]
    10. 8.10 Timing and Switching Characteristics
      1. 8.10.1  Antenna Radiation Patterns
        1. 8.10.1.1 Antenna Radiation Patterns for Receiver
        2. 8.10.1.2 Antenna Radiation Patterns for Transmitter
      2. 8.10.2  Antenna Positions
      3. 8.10.3  Power Supply Sequencing and Reset Timing
      4. 8.10.4  Input Clocks and Oscillators
        1. 8.10.4.1 Clock Specifications
      5. 8.10.5  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.10.5.1 Peripheral Description
        2. 8.10.5.2 MibSPI Transmit and Receive RAM Organization
          1. 8.10.5.2.1 SPI Timing Conditions
          2. 8.10.5.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. 8.10.5.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 8.10.5.3 SPI Peripheral Mode I/O Timings
          1. 8.10.5.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (1) (1)
        4. 8.10.5.4 Typical Interface Protocol Diagram (Peripheral Mode)
      6. 8.10.6  LVDS Interface Configuration
        1. 8.10.6.1 LVDS Interface Timings
      7. 8.10.7  General-Purpose Input/Output
        1. 8.10.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      8. 8.10.8  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 8.10.8.1 Dynamic Characteristics for the CANx TX and RX Pins
      9. 8.10.9  Serial Communication Interface (SCI)
        1. 8.10.9.1 SCI Timing Requirements
      10. 8.10.10 Inter-Integrated Circuit Interface (I2C)
        1. 8.10.10.1 I2C Timing Requirements
      11. 8.10.11 Quad Serial Peripheral Interface (QSPI)
        1. 8.10.11.1 QSPI Timing Conditions
        2. 8.10.11.2 Timing Requirements for QSPI Input (Read) Timings
        3. 8.10.11.3 QSPI Switching Characteristics
      12. 8.10.12 ETM Trace Interface
        1. 8.10.12.1 ETMTRACE Timing Conditions
        2. 8.10.12.2 ETM TRACE Switching Characteristics
      13. 8.10.13 Data Modification Module (DMM)
        1. 8.10.13.1 DMM Timing Requirements
      14. 8.10.14 JTAG Interface
        1. 8.10.14.1 JTAG Timing Conditions
        2. 8.10.14.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 8.10.14.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Processor Subsystem
      3. 9.3.3 Automotive Interface
      4. 9.3.4 Host Interface
      5. 9.3.5 Main Subsystem Cortex-R4F
      6. 9.3.6 DSP Subsystem
      7. 9.3.7 Hardware Accelerator
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Channels (Service) for User Application
        1. 9.4.1.1 GP-ADC Parameter
  10. 10Monitoring and Diagnostics
    1. 10.1 Monitoring and Diagnostic Mechanisms
      1. 10.1.1 Error Signaling Module
  11. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Reference Schematic
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tray Information for ALP, 15 × 15 mm

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALP|180
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Revision History

Changes from November 13, 2020 to May 27, 2021 (from Revision * (November 2020) to Revision A (May 2021))

  • Global: Updated/Changed AWR6843AOP device information and document Product Status from "Advanced Information" to "Production Data (PD)" Go
  • Global: Updated/Changed A2D to ADC, Updated/Changed Master Subsystem to Main Subsystem and Masters R4F to MSS R4FGo
  • Device Information: Updated/Added part numbers and Tray/Tape and Reel information". Updated/Changed Description paragraphGo
  • Device Features Comparison: Changed/Updated to include AWR6843AOP product status to PD and included note about LVDS debugGo
  • (Pin Attributes): Updated/Changed table to remove unsupported mux modes Go
  • Power Consumption Summary: Updated/Modified VIOIN current consumption value (changing from a TYP to a MAX value of 50 mA)Go
  • RF Specification: Updated/Changed Reciever Effective isotropic noise figure (EINF) TYP value from 14 to 9 dB and added Transmitter Power backoff range row Go
  • Antenna radiation patterns: Updated/Changed RX and TX radiation pattern figures Go
  • Transmit Subsystem: Updated/Changed figure.Go
  • Receive Subsystem: Updated/Changed figure.Go
  • Packaging Information: Updated/Added note on the expected variability in the color of the AOP productGo
  • Tray Information for ALP, 15 × 15 mm: Added tray information.Go

Changes from May 28, 2021 to June 1, 2021 (from Revision A (May 2021) to Revision B (June 2021))

  • Global: Updated/Changed CAN to CAN-FDGo
  • (Pin Functions): Updated "CAN_FD_RX" to "CAN1_FD_RX" and added a row for signal name "CAN2_FD_RX" to the list and reassociated ball no. D2Go
  • (Pin Functions): Updated "CAN_FD_TX" to "CAN1_FD_TX" and added a row for signal name "CAN2_FD_TX" to the list and reassociated ball no. B4Go
  • (Pin Attributes): Updated/Changed ball number B4 to show correct signal name as "CAN2_FD_TX"Go
  • (Pin Attributes): Updated/Changed ball number D2 to show correct signal name as "CAN2_FD_RX"Go
  • (Pin Attributes): Updated/Changed signal name from "CAN_FD_RX" to "CAN1_FD_RX'Go
  • (Pin Attributes): Updated/Changed signal name from "CAN_FD_TX" to "CAN1_FD_TX'Go
  • Removed External Clock Electrical Characteristics tableGo
  • Updated/Changed External Clock Mode Specifications table to match AWR16Go
  • Updated/changed the CAN-FD descriptionGo
  • Updated/changed "CAN_FD_rx" to "CANx_FD_RX" and "CAN_FD_tx" to "CANx_FD_TX" in the table to include both instancesGo
  • Updated/Changed Host Interrupt bullet in Host InterfaceGo
  • Updated/Changed text from "ADC channel mapped to B12" to "GPADC channel 6"Go
  • (GP-ADC Parameter): Updated/Changed GP-ADC Parameter table to match AWR16Go
  • Updated/changed "CAN" to "CAN-FD"Go
  • (Monitoring and Diagnostic Mechanisms): Updated/Changed table header and description to reflect Functional Safety-Compliance; added a note for reference to safety related collateral Go
  • Section 13.2 (Tray Information for ABL, 10.4 × 10.4 mm): Added new section with tray information.Go

Changes from June 2, 2021 to July 31, 2022 (from Revision B (June 2021) to Revision C (July 2022))

  • (Features) : Updated Functional-Safety Compliance Certification Collateral; Details on Device Security added; Mentioned the specific operating temperature range for the mmWave SensorGo
  • (Description): Updated/Changed Description to add more details about the device subsystems.Go
  • (Device Comparison) Removed information on Functional-Safety compliance from the table and instead added a table-note for this and LVDS Interface; Additional information on Device security updated.Go
  • (QSPI Timings):Updated/Changed Setup Time from 7.3us to 5us and Hold Time from 1.5us to 1us for QSPI TimingsGo
  • (QSPI Timings): Updated/Changed Delay time, sclk falling edge to d[1] transition i.e. [Q6, Q9] from -3.5us to -2.5us (Min) and 7us to 4us (Max) in QSPI Switching CharacteristicsGo
  • (Monitoring and Diagnostic Mechanisms): Updated/Changed table header and description to reflect Functional Safety-Compliance; added a note for reference to safety related collateral Go
  • (Monitoring and Diagnostic Mechanisms): Updated/Changed table header and description to reflect Functional Safety-Compliance; added a note for reference to safety related collateral Go