SWRS325 December   2024 AWRL6844

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configurations and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Signal Descriptions
      1.      11
      2.      12
      3.      13
      4.      14
      5.      15
      6.      16
      7.      17
      8.      18
      9.      19
      10.      20
      11.      21
      12.      22
      13.      23
      14.      24
      15.      25
      16.      26
      17.      27
    3.     28
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.5.2 Hardware Requirements
      3. 7.5.3 Impact to Your Hardware Warranty
    6. 7.6  Power Supply Specifications
      1. 7.6.1 3.3V I/O Topology
      2. 7.6.2 1.8V I/O Topology
      3. 7.6.3 System Topologies
        1. 7.6.3.1 I/O Topologies
      4. 7.6.4 RF Supply Decoupling Capacitor and Layout Conditions
        1. 7.6.4.1 1.2V RF Supply Rail
          1. 7.6.4.1.1 1.2V RF Rail
        2. 7.6.4.2 1.0V RF LDO
          1. 7.6.4.2.1 1.0V RF LDO
      5. 7.6.5 Noise and Ripple Specifications
    7. 7.7  Power Save Modes
      1. 7.7.1 Typical Power Consumption Numbers
    8. 7.8  Peak Current Requirement per Voltage Rail
    9. 7.9  RF Specification
    10. 7.10 Supported DFE Features
    11. 7.11 CPU Specifications
    12. 7.12 Thermal Resistance Characteristics
    13. 7.13 Timing and Switching Characteristics
      1. 7.13.1  Power Supply Sequencing and Reset Timing
      2. 7.13.2  Synchronized Frame Triggering
      3. 7.13.3  Input Clocks and Oscillators
        1. 7.13.3.1 Clock Specifications
      4. 7.13.4  MultiChannel buffered / Standard Serial Peripheral Interface (McSPI)
        1. 7.13.4.1 McSPI Features
        2. 7.13.4.2 SPI Timing Conditions
        3. 7.13.4.3 SPI—Controller Mode
          1. 7.13.4.3.1 Timing and Switching Requirements for SPI - Controller Mode
          2. 7.13.4.3.2 Timing and Switching Characteristics for SPI Output Timings—Controller Mode
        4. 7.13.4.4 SPI—Peripheral Mode
          1. 7.13.4.4.1 Timing and Switching Requirements for SPI - Peripheral Mode
          2. 7.13.4.4.2 Timing and Switching Characteristics for SPI Output Timings—Secondary Mode
      5. 7.13.5  LVDS Instrumentation and Measurement Peripheral
        1. 7.13.5.1 LVDS Interface Configuration
        2. 7.13.5.2 LVDS Interface Timings
      6. 7.13.6  LIN
      7. 7.13.7  General-Purpose Input/Output
        1. 7.13.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      8. 7.13.8  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.13.8.1 Dynamic Characteristics for the CANx TX and RX Pins
      9. 7.13.9  Serial Communication Interface (SCI)
        1. 7.13.9.1 SCI Timing Requirements
      10. 7.13.10 Inter-Integrated Circuit Interface (I2C)
        1. 7.13.10.1 I2C Timing Requirements
      11. 7.13.11 Quad Serial Peripheral Interface (QSPI)
        1. 7.13.11.1 QSPI Timing Conditions
        2. 7.13.11.2 Timing Requirements for QSPI Input (Read) Timings
        3. 7.13.11.3 QSPI Switching Characteristics
      12. 7.13.12 JTAG Interface
        1. 7.13.12.1 JTAG Timing Conditions
        2. 7.13.12.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 7.13.12.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1  RF and Analog Subsystem
      2. 8.3.2  Clock Subsystem
      3. 8.3.3  Transmit Subsystem
      4. 8.3.4  Receive Subsystem
      5. 8.3.5  Processor Subsystem
      6. 8.3.6  Automotive Interface
      7. 8.3.7  Host Interface
      8. 8.3.8  Application Subsystem Cortex-R5F
      9. 8.3.9  DSP Subsystem
      10. 8.3.10 Hardware Accelerator (HWA1.2) Features
        1. 8.3.10.1 Hardware Accelerator Feature Differences Between HWA1.1 in xWRx843, HWA1.2 in xWRLx432 and HWA1.2 in xWRL684x
    4. 8.4 Other Subsystems
      1. 8.4.1 Security – Hardware Security Module
      2. 8.4.2 GPADC Channels (Service) for User Application
      3. 8.4.3 GPADC Parameters
    5. 8.5 Memory Partitioning Options
    6. 8.6 Boot Modes
  10. 9 Monitoring and Diagnostics
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • ANC|207
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 6-19 Pin Attributes (PKG1 Package)
BGA BALL NUMBER(1) BALL NAME(2) SIGNAL NAME(3) PINCNTL REGISTER(4) PINCNTL REGISTER ADDRESS(5)(11) MODE(6) TYPE(7) PULL UP/DOWN TYPE(8) BALL STATE DURING RST(9) BALL RESET AFTER RST(10)
U12 CAN_FD_B_rx CAN_FD_B_rx PADAY_CFG_REG 0x5A00 0060 0 I PU/PD Off / Off / Off Off / Off / Off
HWASS_UARTA_rx 1 I
ePWMa 2 O
GPIO_0 3 IO
R11 CAN_FD_B_tx CAN_FD_B_tx PADAZ_CFG_REG 0x5A00 0064 0 O PU/PD Off / Off / Off Off / Off / Off
HWASS_UARTA_tx 1 O
ePWMb 2 O
GPIO_1 3 IO
sys_reset_out 4 O
B1 CLKM CLKM A
D1 CLKP CLKP A
T4 GPADC1 GPADC1 A
T3 GPADC2 GPADC2 A
U2 GPADC3 GPADC3 A
U3 GPADC4 GPADC4 A
F16 GPIO_2 GPIO_2 PADAL_CFG_REG 0x5A00 002C 0 IO PU/PD Off / Off / Off Off / Off / Off
LIN_rxLIN_rx 1 I
sys_reset_out 2 O
I2C_sda 3 IO
SPIA_cs1_n 4 IO
RSVD 5 I
RTC_CLK_in 6 I
U16 GPIO_5 GPIO_5 PADAV_CFG_REG 0x5A00 0054 0 IO PU/PD Off / Off / Off Off / Off / Off
SYNC_in 1 I
LIN_rLIN_rx 2 I
ePWMb 3 O
ePWMSYNCI 4 I
C16 HOST_CLK_req HOST_CLK_req(12) PADAX_CFG_REG 0x5A00 005C 0 O PU/PD Off / Off / Off Off / SS / Off
GPIO_7 1 IO
MCU_CLKOUT(12) 2 O
LIN_txLIN_tx 3 O
RSVD 4 I
SPIB_miso 5 IO
I2C_scl 6 IO
N16 I2C_scl I2C_scl PADBC_CFG_REG 0x5A00 0070 0 IO PU/PD Off / Off / Off Off / Off / Off
PMIC_CLKOUT 1 O
UARTA_rx 2 I
GPIO_4 3 IO
RSVD 4 O
ePWMa 5 O
ePWMSYNCI 6 I
SPIB_clk 7 IO
N17 I2C_sda I2C_sda PADBD_CFG_REG 0x5A00 0074 0 IO PU/PD Off / Off / Off Off / Off / Off
MCU_CLKOUT 1 O
UARTA_tx 2 O
GPIO_5 3 IO
RSVD 4 O
ePWMb 5 O
ePWMSYNCO 6 O
SPIB_cs1_n 7 IO
SPIB_mosi 8 IO
U13 LIN_rx LIN_rx PADBE_CFG_REG 0x5A00 0078 0 I PU/PD Off / Off / Off Off / Off / Off
UARTB_tx 1 O
GPIO_6 2 IO
T11 LIN_tx LIN_tx PADBF_CFG_REG 0x5A00 007C 0 O PU/PD Off / Off / Off Off / Off / Off
UARTB_rx 1 I
GPIO_7 2 IO
PRCM_PMIC_DeepSleep 3 O
P16 lvds_valid LVDS_VALID PADBA_CFG_REG 0x5A00 0068 0 O PU/PD Off / Off / Off Off / Off / Off
nERROR_OUT 1 O
LIN_rxLIN_rx 2 I
GPIO_2 3 IO
RSVD 4 O
SPIA_cs1_n 5 IO
SPIB_miso 6 IO
SPIB_clk 7 IO
SYNC_in 8 I
PRCM_PMIC_DeepSleep 9 O
N15 nERROR_OUT nERROR_OUT PADAU_CFG_REG 0x5A00 0050 0 O PU/PD Off / Off / Off Off / Off / Off
GPIO_4 1 IO
SYNC_in 2 I
SPIB_cs0_n 3 IO
WU_reqin 4 I
RTC_CLK_in 5 I
MCU_CLKOUT 6 O
U10 NRESET NRESET A
F7 OSC_CLK_OUT OSC_CLK_OUT A
C17 PMIC_CLKOUT SOP[1] PADAK_CFG_REG 0x5A00 0028 During Power-Up I PU/PD Off / Off / Off Off / Off / Off
PMIC_CLKOUT(12) 0 O
LIN_txLIN_tx 1 O
SPIA_cs1_n 2 IO
B14 QSPI_clk QSPI_clk PADAA_CFG_REG 0x5A00 0000 0 IO PU/PD Off / Off / Off Off / Off / Off
SPIB_clk 1 IO
A13 QSPI_cs_n QSPI_cs_n PADAB_CFG_REG 0x5A00 0004 0 O PU/PD Off / Off / Off Off / Off / Off
SPIB_cs0_n 1 IO
B13 QSPI_din QSPI_din PADAD_CFG_REG 0x5A00 000C 0 I PU/PD Off / Off / Off Off / Off / Off
SPIB_miso 1 IO
RTC_CLK_in 2 I
A12 QSPI_dout QSPI_dout PADAC_CFG_REG 0x5A00 0008 0 IO PU/PD Off / Off / Off Off / Off / Off
SPIB_mosi 1 IO
B12 QSPI_qdin0 QSPI_qdin0 PADAE_CFG_REG 0x5A00 0010 0 I PU/PD Off / Off / Off Off / Off / Off
I2C_scl 1 IO
WU_reqin 2 I
B11 QSPI_qdin1 QSPI_qdin1 PADAF_CFG_REG 0x5A00 0014 0 I PU/PD Off / Off / Off Off / Off / Off
I2C_sda 1 IO
SYNC_in 2 I
R14 rs232_rx rs232_rx PADAP_CFG_REG 0x5A00 003C 0 I PU/PD Off / Off / Up On / Off / Up
I2C_sda 1 IO
UARTB_rx 2 I
LIN_rxLIN_rx 3 I
RSVD 4 O
SPIB_miso 5 IO
HWASS_UARTA_rx 6 I
P15 rs232_tx rs232_tx PADAO_CFG_REG 0x5A00 0038 0 O PU/PD Off / Off / Off Off / SS / Off
I2C_scl 1 IO
UARTB_tx 2 O
LIN_txLIN_tx 3 O
ePWMSYNCI 4 I
RSVD 5 O
SPIB_cs1_n 6 IO
HWASS_UARTA_tx 7 O
N1 RX1 RX1 A
L1 RX2 RX2 A
J1 RX3 RX3 A
G1 RX4 RX4 A
A16 SPIA_clk SPIA_clk PADAG_CFG_REG 0x5A00 0018 0 IO PU/PD Off / Off / Off Off / Off / Off
ePWMb 1 O
I2C_scl 2 IO
SPIB_clk 3 IO
B17 SPIA_cs0_n SPIA_cs0_n PADAH_CFG_REG 0x5A00 001C 0 IO PU/PD Off / Off / Off Off / Off / Off
ePWMa 1 O
I2C_sda 2 IO
SPIB_cs0_n 3 IO
B15 SPIA_miso SPIA_miso PADAJ_CFG_REG 0x5A00 0024 0 IO PU/PD Off / Off / Off Off / Off / Off
GPIO_1 1 IO
ePWMa 2 O
SPIB_miso 3 IO
A15 SPIA_mosi SPIA_mosi PADAI_CFG_REG 0x5A00 0020 0 IO PU/PD Off / Off / Off Off / Off / Off
GPIO_0 1 IO
ePWMb 2 O
SPIB_mosi 3 IO
RSVD 4 O
LVDS_VALID 5 O
R16 sys_reset_out sys_reset_out PADBB_CFG_REG 0x5A00 006C 0 O PU/PD Off / Off / Off Off / Off / Off
WU_reqin 1 I
LIN_txLIN_tx 2 O
GPIO_3 3 IO
RSVD 4 O
SPIB_cs0_n 5 IO
T12 TCK TCK PADAT_CFG_REG 0x5A00 004C 0 I PU/PD Off / Off / Down On / Off / Down
ePWMb 1 O
T14 TDI TDI PADAR_CFG_REG 0x5A00 0044 0 I PU/PD Off / Off / Down On / Off / Down
ePWMa 1 O
T13 TDO SOP[0] PADAS_CFG_REG 0x5A00 0048 During Power-Up I PU/PD Off / Off / Off Off / SS / Off
TDO 0 O
T15 TMS TMS PADAQ_CFG_REG 0x5A00 0040 0 I PU/PD Off / Off / Up On / Off / Up
sys_reset_out 1 O
RSVD 2
RSVD 3
RSVD 4
RSVD 5
RTC_CLK_in 6 I
ePWMSYNCI 7 I
ePWMSYNCO 8 O
A3 TX1 TX1 A
A5 TX2 TX2 A
A7 TX3 TX3 A
A9 TX4 TX4 A
U15 UARTA_rts UARTA_rts PADAW_CFG_REG 0x5A00 0058 0 O PU/PD Off / Off / Off Off / Off / Off
GPIO_6 1 IO
LIN_txLIN_tx 2 O
RSVD 3
WU_reqin 4 I
ePWMa 5 O
RTC_CLK_in 6 I
R10 UARTA_rx UARTA_rx PADAM_CFG_REG 0x5A00 0030 0 I PU/PD Off / Off / Off Off / Off / Off
GPIO_3 1 IO
LIN_rxLIN_rx 2 I
CAN_FD_rx 3 I
SYNC_in 4 I
UARTB_rx 5 I
I2C_sda 6 IO
RSVD 7 O
HWASS_UARTA_rx 8 I
T10 UARTA_tx UARTA_tx PADAN_CFG_REG 0x5A00 0034 0 O PU/PD Off / Off / Off Off / Off / Off
LIN_txLIN_tx 1 O
CAN_FD_tx 2 O
RSVD 3
WU_reqin 4 I
UARTB_tx 5 O
I2C_scl 6 IO
RSVD 7 O
HWASS_UARTA_tx 8 O
K3 VBGAP VBGAP A
E13, E14, F10, F11, F12, F13, F14, F9, G10, G11, G12, G13, G14, G9, H10, H11, H12, H13, H14, H9, T5, U5 VDD VDD PWR
D5, D6, D7, K5 VDDA_10RF VDDA_10RF PWR
D10, D8, D9 VDDA_12RF VDDA_12RF PWR
R1, R2 VDDA_18BB VDDA_18BB PWR
G3 VDDA_18VCO VDDA_18VCO PWR
T9, U9 VDD_SRAM VDD_SRAM PWR
M4 VIN_18PM VIN_18PM PWR
D17, T17, U6 VIOIN VIOIN PWR
F17, R17, U8 VIOIN_18 VIOIN_18 PWR
D3 VIOIN_18CLK VIOIN_18CLK PWR
K16 VIOIN_18LVDS VIOIN_18LVDS PWR
T6 VNWA VNWA PWR
H7 VOUT_14APLL VOUT_14APLL PWR
F3 VOUT_14SYNTH VOUT_14SYNTH PWR
R4 VPP VPP PWR
A17, B16, D16, E10, E11, E12, E16, J10, J11, J12, J13, J14, J16, J9, K10, K11, K12, K13, K14, K7, K8, K9, L10, L11, L12, L13, L14, L7, L8, L9, M10, M11, M12, M13, M14, M7, M8, M9, N10, N11, N12, N13, N14, N7, N8, N9, T16, T7, T8, U17 VSS VSS GND
A1, A10, A2, A4, A6, A8, B10, B2, B3, B4, B5, B6, B7, B8, B9, C1, C2, D2, E1, E2, E7, E8, E9, F1, F2, F8, G2, G7, G8, H1, H2, H8, J2, J7, J8, K1, K2, K6, L2, L5, L6, M1, M2, M5, M6, N2, N5, N6, P1, P2, T1, T2, U1 VSSA VSSA GND
(1) BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.
(2) BALL NAME: Mechanical name from package device (name is taken from muxmode 0).
(3) SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).
(4) PINCNTL_REGISTER: APPSS Register name for PinMux Control
(5) PINCNTL ADDRESS: APPSS Address for PinMux Control
(6) MODE: Multiplexing mode number: value written to PinMux Cntl register to select specific Signal name for this Ball number. Mode column has bit range value.
(7) TYPE: Signal type and direction:
  • I = Input
  • O = Output
  • IO = Input or Output
(8) PULL UP/DOWN TYPE: indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.
  • Pull Up: Internal pullup
  • Pull Down: Internal pulldown
  • An empty box means No pull.
(9) BALL STATE DURING RST: State of Ball during reset in the format of RX/TX/Pull Status
  • RX (Input buffer)
    • Off: The input buffer is disabled.
    • On: The input buffer is enabled.
  • TX (Output buffer)
    • Off: The output buffer is disabled.
    • Low: The output buffer is enabled and drives VOL.
  • Pull Status (Internal pull resistors)
    • Off: Internal pull resistors are turned off.
    • Up: Internal pull-up resistor is turned on.
    • Down: Internal pull-down resistor is turned on.
    • NA: No internal pull resistor.
  • An empty box, or "-" means Not Applicable.
(10) BALL STATE AFTER RST: State of Ball after reset in the format of RX/TX/Pull Status
  • RX (Input buffer)
    • Off: The input buffer is disabled.
    • On: The input buffer is enabled.
  • TX (Output buffer)
    • Off: The output buffer is disabled.
    • SS: The subsystem selected with MUXMODE determines the output buffer state.
  • Pull status (Internal pull resistors)
    • Off: Internal pull resistors are turned off.
    • Up: Internal pull-up resistor is turned on.
    • Down: Internal pull-down resistor is turned on.
    • NA: No internal pull resistor.
  • An empty box, NA, or "-" means Not Applicable.
(11) Pin Mux Control Value maps to lower 4 bits of register.
(12) Restricted use. Not available during deepsleep