SLUSFR2 November   2024 BQ21088

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Battery Charging Process
        1. 7.1.1.1 Trickle Charge
        2. 7.1.1.2 Pre-Charge
        3. 7.1.1.3 Fast Charge
        4. 7.1.1.4 Termination
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Based Dynamic Power Management (VINDPM)
      2. 7.3.2  Dynamic Power Path Management Mode (DPPM)
      3. 7.3.3  Battery Supplement Mode
      4. 7.3.4  Sleep Mode
      5. 7.3.5  SYS Power Control (SYS_MODE bit control)
        1. 7.3.5.1 SYS Pulldown Control
      6. 7.3.6  SYS Regulation
      7. 7.3.7  ILIM Control
      8. 7.3.8  Protection Mechanisms
        1. 7.3.8.1 Input Overvoltage Protection
        2. 7.3.8.2 Battery Undervoltage Lockout
        3. 7.3.8.3 Battery Overcurrent Protection
        4. 7.3.8.4 System Overvoltage Protection
        5. 7.3.8.5 System Short Protection
        6. 7.3.8.6 Thermal Protection and Thermal Regulation
        7. 7.3.8.7 Safety Timer and Watchdog Timer
      9. 7.3.9  Pushbutton Wake and Reset Input
        1. 7.3.9.1 Pushbutton Wake or Short Button Press Functions
        2. 7.3.9.2 Pushbutton Reset or Long Button Press Functions
      10. 7.3.10 15-Second Timeout for HW Reset
      11. 7.3.11 Hardware Reset
      12. 7.3.12 Software Reset
      13. 7.3.13 Interrupt Indicator (/INT) Pin
      14. 7.3.14 External NTC Monitoring (TS)
        1. 7.3.14.1 TS Biasing and Function
      15. 7.3.15 I2C Interface
        1. 7.3.15.1 F/S Mode Protocol
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
      1. 7.5.1 I2C Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YBG|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.15 I2C Interface

The device uses an I2C compatible interface to program and read control parameters, status bits, etc. I2C ™ is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device.

The device works as a preipheral and supports the following data transfer modes, as defined in the I2C Bus™ Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the battery charge solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements.

Register contents remain intact as long as VBAT or VIN voltages remains above their respective undervoltage lockout thresholds and the device is not in shutdown mode.

The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the F/S-mode in this document. The device only supports 7-bit addressing. The device 7-bit address is 0x6A (8-bit shifted address is 0xD4).