SLUSFR2 November   2024 BQ21088

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Battery Charging Process
        1. 7.1.1.1 Trickle Charge
        2. 7.1.1.2 Pre-Charge
        3. 7.1.1.3 Fast Charge
        4. 7.1.1.4 Termination
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Based Dynamic Power Management (VINDPM)
      2. 7.3.2  Dynamic Power Path Management Mode (DPPM)
      3. 7.3.3  Battery Supplement Mode
      4. 7.3.4  Sleep Mode
      5. 7.3.5  SYS Power Control (SYS_MODE bit control)
        1. 7.3.5.1 SYS Pulldown Control
      6. 7.3.6  SYS Regulation
      7. 7.3.7  ILIM Control
      8. 7.3.8  Protection Mechanisms
        1. 7.3.8.1 Input Overvoltage Protection
        2. 7.3.8.2 Battery Undervoltage Lockout
        3. 7.3.8.3 Battery Overcurrent Protection
        4. 7.3.8.4 System Overvoltage Protection
        5. 7.3.8.5 System Short Protection
        6. 7.3.8.6 Thermal Protection and Thermal Regulation
        7. 7.3.8.7 Safety Timer and Watchdog Timer
      9. 7.3.9  Pushbutton Wake and Reset Input
        1. 7.3.9.1 Pushbutton Wake or Short Button Press Functions
        2. 7.3.9.2 Pushbutton Reset or Long Button Press Functions
      10. 7.3.10 15-Second Timeout for HW Reset
      11. 7.3.11 Hardware Reset
      12. 7.3.12 Software Reset
      13. 7.3.13 Interrupt Indicator (/INT) Pin
      14. 7.3.14 External NTC Monitoring (TS)
        1. 7.3.14.1 TS Biasing and Function
      15. 7.3.15 I2C Interface
        1. 7.3.15.1 F/S Mode Protocol
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
      1. 7.5.1 I2C Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YBG|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

BQ21088 YBG Package WCSP 8 Pin (Top View)Figure 5-1 YBG Package WCSP 8 Pin (Top View)
Table 5-1 Pin Functions
PINI/O(1)DESCRIPTION
NAMENO.
IN A2 P DC Input Power Supply. IN is connected to the external DC supply. Bypass IN to GND with at least 1 μF of effective capacitance using a ceramic capacitor.
SYS B2 P Regulated System Output. Connect at least 10-μF ceramic capacitor (at least 1 μF of ceramic capacitance with DC bias de-rating) from SYS to GND as close to the SYS and GND pins as possible.
BAT C2 P Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with at least 1 μF of ceramic capacitance.
GND D2 - Ground connection. Connect to the ground plane of the circuit.
SCL B1 I/O I2C Interface Clock. Connect SCL to the logic rail through a 10-kΩ resistor.
SDA C1 I/O I2C Interface Data. Connect SDA to the logic rail through a 10-kΩ resistor.
/INT A1 O INT is an open-drain output that signals fault interrupts. When a fault occurs, a 128-μs active low pulse is sent out as an interrupt for the host. INT is enabled/disabled using the MASK_INT bit in the control register. Can be pulled up to a 1- to 20-kΩ resistor. Typical pull-up voltage = 1.8 V, max pull-up voltage = 5 V.
TS/MR D1 I/O Manual Reset Input/ NTC thermistor pin. TSMR is a general purpose input that must be held low for greater than tLPRESS to go into Shipmode or perform a hardware reset. It can also be used to detect shorter button press durations such as twake1 and twake2 TSMR may be driven by a momentary push-button or a MOS switch. The TSMR pin will also have an NTC thermistor connected on to it.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.