11.1 Layout Guidelines

• For optimal performance, place the decoupling capacitor from the input terminal to VSS and the output filter capacitor from OUT to VSS as close as possible to the bq2407x, with short trace runs to both signal and VSS pins.
• Keep all low-current VSS connections separate from the high-current charge or discharge paths from the battery. Use a single-point ground technique incorporating the small signal ground path and the power ground path.
• The high-current charge paths into IN and from the BAT and OUT pins must be sized appropriately for the maximum charge current to avoid voltage drops in these traces.
• The bq2407x is packaged in a thermally enhanced MLP package. The MLP package includes a QFN thermal pad to provide an effective thermal contact between the device and the printed-circuit board (PCB). For detailed PCB design guidelines for this package, see the QFN/SON PCB Attachment Application Note (SLUA271).

The recommend layout is shown in Figure 11.

11.2 Layout Example

Figure 11. Recommended Layout

11.3 Thermal Considerations

The bq2407x is packaged in a thermally enhanced MLP package. The package includes a QFN thermal pad to provide an effective thermal contact between the device and the printed-circuit board (PCB). Full PCB design guidelines for this package are provided in the application note entitled QFN/SON PCB Attachment (SLUA271). The power pad should be tied to the VSS plane. The most common measure of package thermal performance is thermal impedance (θ_JA) measured (or modeled) from the chip junction to the air surrounding the package surface (ambient).

The mathematical expression for θ_JA is:

Equation 9.

where

• T_J = chip junction temperature
• T_A = ambient temperature
• P = device power dissipation

Factors that can greatly influence the measurement and calculation of θ_JA include:

• whether or not the device is board mounted
• trace size, composition, thickness, and geometry
• orientation of the device (horizontal or vertical)
• volume of the ambient air surrounding the device under test and airflow
• whether other surfaces are in close proximity to the device being tested

The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal power FET. It can be calculated from Equation 10:

Equation 10.

Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of the charge cycle when the battery voltage is at its lowest. See Figure 2. Typically the voltage of the Li-ion battery quickly (< 2 V minutes) ramps to approximately 3.5 V, when entering fast charge (1-C charge rate and battery above 3 V). Therefore, it is customary to perform the steady-state thermal design using 3.5 V as the minimum battery voltage because the system board and charging device does not have time to reach a maximum temperature due to the thermal mass of the assembly during the early stages of fast charge. This theory is easily verified by performing a charge cycle on a discharged battery while monitoring the battery voltage and chargers power pad temperature.